Dummy Metal Gate Features for CMP Uniformity in CMOS Fabrication
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Solution Overview
Problem
In the fabrication of complementary metal-oxide-semiconductor (CMOS) integrated circuits, the 'gate last' process faces challenges with non-uniform distribution of metal gate features during chemical-mechanical polishing, leading to device instability and potential failure, especially as feature sizes decrease.
Innovation Solution
The method involves forming dummy metal gate features within an insulation layer to optimize the distribution of metal gate electrodes, controlling the gate area ratio to prevent loading effects during CMP processes, thereby ensuring uniformity and stability of metal gate features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate last process is used to form metal gate features, then the number of subsequent high temperature processing steps is reduced, but non-uniform distribution of metal gate features occurs during CMP process
Solution Approach 1:
The patent forms dummy gate features before the actual gate formation process. These dummy features are created in advance to establish a uniform distribution pattern across the substrate, which then guides the subsequent formation of real metal gate features, ensuring uniformity is achieved before the gate last process begins
Solution Approach 2:
The patent modifies the distribution parameters of gate features by introducing dummy features with specific spacing and sizing. This changes the physical parameters of the gate feature distribution, creating a more uniform pattern that maintains consistency during the CMP process while still allowing the gate last process to proceed
2Productivity
If gate length and spacing between devices are decreased, then device density is improved, but loading effects during CMP process increase
Solution Approach 1:
The patent segments the gate features into two categories: actual functional gates and dummy gates. This segmentation allows the dummy gates to be specifically designed for spacing and distribution purposes, while the actual gates maintain their functional requirements. The segmented approach enables independent optimization of each type
Solution Approach 2:
The dummy gate features act as intermediaries between the actual gate features and the CMP process. They serve as a buffer that absorbs the loading effects during polishing, protecting the actual small-sized gates from instability while maintaining the high device density required for modern processors
Data Source
AI summary
A method of making a semiconductor device includes etching an insulation layer to form a plurality of openings over a first region of the substrate and a plurality of openings over a second region of the substrate. The method includes filling a first opening of the plurality of openings over the first region with a first P-metal. The method includes filling a second opening of the plurality of openings over the first region with a first N-metal. An area of the first N-metal substantially differs in size from an area of the first P-metal. The method includes filling a first opening of the plurality of openings over the second region with a second P-metal. The method includes filling a second opening of the plurality of openings over the second region with a second N-metal. An area of the second N-metal differs from an area of the second P-metal.