Dummy Metal Layer Stack Around Sensing Region for Clean Chip Singulation
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Solution Overview
Problem
The chip packaging process faces challenges due to the brittleness and thermal sensitivity of low-k dielectric materials, leading to defects such as debris, cracks, and rough sidewalls during singulation.
Innovation Solution
A method for forming a chip package that includes a substrate with a chip region and a scribe-line region, a dielectric layer with a dummy structure comprising concentric stacks of dummy metal layers, and a sawing process that forms a saw opening through the dielectric layer while leaving the dummy metal layers intact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a sawing process is performed on the dielectric layer during singulation, then individual chip packages can be formed, but debris, cracks, and rough sidewalls occur due to the brittleness of low-k dielectric material
Solution Approach 1:
A dummy structure is formed in the dielectric layer before the sawing process. This dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside, positioned over the scribe-line region and extending along edges of the chip region. The dummy structure acts as a protective barrier that prevents cracks and debris from propagating into the chip region during subsequent sawing operations.
Solution Approach 2:
The dummy structure serves as an intermediary element between the saw blade and the chip region. It absorbs the mechanical stress and debris generated during sawing, protecting the actual chip structure. The dummy structure includes sacrificial metal layers that can be selectively removed after serving their protective function.
2Reliability
If the dielectric layer is made of low-k material to reduce signal interference, then electrical performance is improved, but mechanical strength and thermal stability deteriorate
Solution Approach 1:
The solution combines low-k dielectric material with a composite dummy structure consisting of multiple metal layers (first stack and second stack) and dielectric material. This composite structure provides both the electrical benefits of low-k material and the mechanical strength needed to withstand processing operations. The dummy metal layers add structural reinforcement without compromising the electrical performance of the actual chip region.
Data Source
AI summary
Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.