Dummy Metallization Pattern for Plasma-Safe Gate Interconnects

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in maintaining the integrity of integrated circuit devices during manufacturing processes, particularly due to plasma-induced damage (PID) that can degrade channel resistance in transistors.

Innovation Solution

The introduction of a dummy conductive pattern in the metallization structure of integrated circuit devices serves as a charge pool to relax plasma-induced charges, thereby reducing the risk of damage to the transistor nanostructures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If plasma processing is used in manufacturing, then manufacturing productivity is improved, but plasma-induced damage degrades transistor channel resistance

Engineering Contradiction:

Improvemanufacturing productivityVSAvoidtransistor channel resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The dummy conductive pattern serves as an intermediary charge pool between the plasma processing environment and the transistor gate structure. It absorbs excess plasma-induced charges that would otherwise damage the transistor channel, thereby protecting the transistor while allowing plasma processing to continue for high productivity

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention converts the harmful plasma-induced charges into a beneficial effect by using the dummy conductive pattern to collect and neutralize these charges. What would normally be damage (plasma-induced positive charges) is transformed into a controlled charge management mechanism that protects the transistor

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively mitigates plasma-induced damage, preserving the channel resistance of transistors and ensuring the reliability of integrated circuit devices.

Implementation Method 1

plasma-induced damage (PID) that can degrade channel resistance in transistors

Methodology Applied

Scientific EffectPlasma: Plasma

Implementation Method 2

serves as a charge pool to relax plasma-induced charges

Methodology Applied

Scientific EffectCharge relaxation:

Data Source

PatentUS20250098255A1Integrated circuit device and manufacturing method thereof

Publication Date: 2025.03.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit device includes a transistor, a dielectric layer, a first vertical connecting structure. The transistor includes a gate structure. The dielectric layer surrounds the transistor. The first vertical connecting structure extends through the dielectric layer. The gate contact via is over the gate structure. The front-side metallization pattern is over the transistor. The front-side metallization pattern includes a first conductive path and a dummy conductive pattern. The first conductive path connects the gate contact via to a top end of the first vertical connecting structure. The dummy conductive pattern is connected to the first conductive path. The back-side metallization layer is below the transistor, wherein the back-side metallization layer is connected with a bottom end of the first vertical connecting structure.