Dummy MOSFET Circuit for Core Transistor SOA Voltage Management

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Solution Overview

Problem

Semiconductor devices face limitations in operating at the same voltage as input/output devices due to differences in voltage requirements and performance characteristics, restricting their applications and operating speed.

Innovation Solution

Incorporating dummy devices with specific transistor configurations and voltage management circuits that allow core devices to operate within the safe operating area (SOA) across a range of voltages, including those of input/output devices, by using n-channel and p-channel MOSFETs with tailored threshold voltages and connections to manage voltage levels and reduce leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If core devices are operated at higher voltage (IO device voltage level) to improve operating speed and performance, then the operating speed and driving capability are improved, but the core devices cannot operate safely outside their designed voltage range

Engineering Contradiction:
Improveoperating speedVSAvoidsafe operating area compliance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces a voltage management circuit as an intermediary between the core device and the IO device voltage level. This circuit includes a first transistor connected between the core device and a first voltage node, and a second transistor connected between the core device and a second voltage node. These transistors act as mediators that control the voltage applied to the core device, enabling it to operate at higher voltages when needed while preventing damage from excessive voltage, thus resolving the contradiction between speed improvement and safe operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If IO devices are used to operate at higher voltage with better SOA, then the safe operating area is improved, but the operating speed and driving capability deteriorate

Engineering Contradiction:
Improvesafe operating areaVSAvoidoperating speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic voltage management where the voltage applied to the core device can change based on operational requirements. The voltage management circuit dynamically adjusts the voltage level by controlling the switching states of the first and second transistors, allowing the core device to operate at higher voltages for improved speed when needed, while maintaining safety through automatic voltage regulation. This dynamic approach allows the system to achieve both high performance and safe operation.

Inventive Principle:
Principle #15Dynamics

3Reliability

If core devices are designed with thicker oxide structure like IO devices to improve SOA, then the safe operating area is improved, but the performance in terms of operating speed and driving capability is reduced

Engineering Contradiction:
Improvesafe operating areaVSAvoiddriving capability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by using different transistor structures in different locations within the same device. The voltage management circuit uses transistors with specific threshold voltages and structures optimized for voltage control, while the core device maintains its original thin oxide structure for high performance. This localized differentiation allows the core device to maintain its high driving capability and operating speed while the voltage management circuit provides the necessary protection and voltage regulation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12183731B2Dummy device for core device to operate in a safe operating area and method for manufacturing the same
Publication Date: 2024.12.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12183731B2 patent drawing
  • US12183731B2 patent drawing
  • US12183731B2 patent drawing

AI summary

A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor.