Semiconductor Bonding Structure With Dummy Pads for Void-Free Fine Pitch
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high I/O density and fine pitch interconnects due to surface topography deviations in hybrid bonding of semiconductor chip dies, leading to stack voids and limitations in implementing high-density electrical signal connections.
Innovation Solution
The introduction of additional dummy bonding pads spaced apart from conductive pads in a vertical direction, along with via plugs and bonding structures, helps planarize the bonding surface, preventing stack voids and enabling high-density, fine-pitch I/O connections by improving electroplating uniformity and chemical mechanical polishing flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If hybrid bonding is applied to couple semiconductor chip dies, then high I/O density can be achieved, but surface topography deviation causes stack voids and bonding defects
Solution Approach 1:
The patent applies preliminary planarization by forming a first dielectric layer and first bonding pads before the bonding process, then performing chemical mechanical polishing (CMP) to flatten the bonding surface. This preliminary flattening action eliminates surface topography deviations that would otherwise cause stack voids during hybrid bonding, enabling both high I/O density and defect-free bonding.
2Manufacturing precision
If bonding surfaces are flattened to prevent stack voids, then bonding quality improves, but fine pitch I/O implementation is limited due to misalignment of dummy test pad and dummy bonding pad
Solution Approach 1:
The patent introduces second bonding pads that are electrically decoupled from the interconnect structure and positioned at specific locations to provide local planarization support. These second bonding pads create additional flat regions on the bonding surface without interfering with the electrical function of the first bonding pads, enabling both surface flattening and fine pitch I/O implementation.
3Stability of the object's composition
If additional dummy bonding pads are added to planarize the bonding surface, then stacking flatness improves, but device complexity increases
Solution Approach 1:
The patent merges the planarization function with the existing bonding pad structure by forming second bonding pads within the same dielectric layer and bonding surface preparation process. Rather than adding a separate planarization layer or structure, the second bonding pads are integrated into the bonding interface design, achieving stacking flatness while minimizing additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents stack voids and allows for the implementation of high-density, fine-pitch I/O connections, enhancing the bonding surface flatness and electroplating uniformity, thereby improving the semiconductor chip stacking structure's performance.
Implementation Method 1
enhancing the bonding surface flatness and electroplating uniformity
Implementation Method 2
improving electroplating uniformity and chemical mechanical polishing flatness
Data Source
AI summary
A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.