Dummy Pattern Layout in Intermetal Dielectrics to Reduce CMP Dishing
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Solution Overview
Problem
Dishing and erosion effects occur during the planarization of semiconductor devices due to the use of chemical mechanical polishing (CMP) processes on dielectric layers with varying polish rates, leading to uneven surfaces and structural integrity issues.
Innovation Solution
Incorporation of a conductive pattern layout structure in intermetal layers to mitigate dishing and erosion effects by using a dummy pattern structure in the intermetal dielectric layer, which helps in uniform planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) processes are used to planarize dielectric layers, then surface flatness is improved, but dishing and erosion effects occur due to varying polish rates of different materials
Solution Approach 1:
The patent applies local quality by creating dummy patterns with specific conductive materials in regions where dishing and erosion are most severe. These dummy patterns have different polish rates than the surrounding interconnect structures, allowing localized compensation for material removal variations during CMP processing.
Solution Approach 2:
The dummy patterns are designed in advance to counteract the harmful dishing and erosion effects before they fully manifest. By pre-positioning these compensatory structures, the patent creates a preliminary anti-action that offsets the varying polish rates of different materials during the planarization process.
2Manufacturing precision
If dummy pattern structures are added to compensate for dishing and erosion, then surface uniformity is improved, but device complexity increases
Solution Approach 1:
The dummy patterns are simplified copies or replicas of actual interconnect structures, designed to mimic their polish rate characteristics without requiring new materials or complex fabrication steps. This copying approach allows the dummy patterns to be integrated using existing process tools and materials.
Solution Approach 2:
The dummy patterns use the same conductive materials and fabrication processes as the surrounding interconnect structures, maintaining material homogeneity throughout the device. This approach avoids introducing new materials or processes, thereby limiting the increase in device complexity while still achieving surface uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces or eliminates dishing and erosion effects, ensuring a flat and stable surface for bonding, enhancing the structural integrity and performance of semiconductor devices.
Implementation Method 1
The planarization can be achieved by chemical mechanically polishing (CMP) processes
Data Source
AI summary
A method comprises: providing a first die; providing a second die having a planar side surface; and bonding the planar side surface of the second die to a top surface of the first die. The first die comprises: a first substrate; an interlayer dielectric layer; and an intermetal dielectric layer. The intermetal dielectric layer comprises: at least one first dielectric layer comprising a first dielectric constant value; at least one second dielectric layer comprising a second dielectric constant value greater than the first dielectric constant value; and a first dummy pattern comprising a first conductive pattern having a first dummy pattern density in the at least one first dielectric layer and a second conductive pattern having a second dummy pattern density in the at least one second dielectric layer, wherein the first dummy pattern density is greater than the second dummy pattern density.