Dummy Pattern Die for Compact Chip Stack Interconnection
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Solution Overview
Problem
Conventional chip stack packages require increased size due to wire bonding or metal film tape interconnections, leading to enlarged substrates and packages, especially when mounting multiple semiconductor chips.
Innovation Solution
A chip stack package using a dummy pattern die with a via pattern and circuit pattern, connected via solder balls, eliminates the need for extra space by replacing wire bonding or metal film tape, allowing for efficient electrical and mechanical connections between semiconductor chips and the substrate without enlarging the package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to make electrical interconnection between stacked chips and substrate, then electrical connection is achieved, but the substrate size becomes enlarged due to bonding wires running in horizontal and vertical directions
Solution Approach 1:
The patent extracts the bonding pads from the chip surfaces and relocates them to the substrate through dummy pattern dies. This removes the need for wire bonding that extends bonding pads in multiple directions, thereby eliminating the requirement for enlarged substrate area to accommodate horizontal and vertical wire routing.
Solution Approach 2:
The dummy pattern die serves as an intermediary component between the stacked chips and the substrate. It provides a compact electrical interconnection path through vertical vias and circuit patterns, replacing the need for extended wire bonding that would require larger substrate area.
2Reliability
If metal film tape is used for electrical interconnection instead of wire bonding, then connection is achieved, but extra space is necessary to prevent chip interference, enlarging the package size
Solution Approach 1:
The patent extracts the electrical interconnection function from the metal film tape that requires extra space, and relocates it to the dummy pattern die structure. The dummy pattern die with its via pattern and circuit pattern provides electrical connection without requiring the metal film tape to be drawn in one direction with extra space for chip clearance.
Solution Approach 2:
The patent transitions from a planar metal film tape interconnection (requiring horizontal space) to a vertical via-based interconnection through the dummy pattern die. This dimensional change from horizontal to vertical routing eliminates the need for extra space to prevent chip interference.
3Reliability
If bonding pads extend in one direction on top of each stacked chip, then electrical connection is established, but the number of bonding wires increases
Solution Approach 1:
The patent merges multiple bonding pad functions into the dummy pattern die structure. Instead of having separate bonding pads on each chip that require individual wire connections, the dummy pattern die consolidates the electrical interconnection through its circuit pattern and via pattern, reducing the number of bonding wires required.
Solution Approach 2:
The dummy pattern die acts as an intermediary that consolidates multiple electrical connection points. It receives connections from stacked chips through its circuit pattern and provides unified interconnection to the substrate, reducing the total number of bonding wires needed compared to direct chip-to-substrate wiring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-capacity chip stack packages of compact size, effective heat dissipation, and improved reliability by eliminating the need for extra space and preventing chip interference, while maintaining compatibility with semiconductor chip expansion coefficients.
Implementation Method 1
first solder balls for electrically connecting the bond finger of the printed circuit board with the circuit pattern of the dummy pattern die while electrically connecting the via pattern of stacked dummy pattern dies with the circuit pattern
Implementation Method 2
a bump interposed between the semiconductor chip and the dummy pattern die so as to electrically and mechanically connect the semiconductor chip with the dummy pattern die
Data Source
AI summary
The chip stack package includes at least a printed circuit board having a bond finger and a ball land, and at least two semiconductor chips stacked on the printed circuit board while being spaced from each other and formed with a plurality of bonding pads. A dummy pattern die is attached to the upper surface of each semiconductor chip. The dummy pattern die is formed with a circuit pattern on its lower surface for electrical connection to the semiconductor chip. The dummy pattern is also formed with a via pattern on its upper side which is connected to the circuit pattern. The first solder balls electrically connects the bond finger with the circuit pattern while electrically connecting the via pattern of stacked dummy pattern dies with the circuit pattern. The second solder balls are attached to the ball land of the printed circuit board.