Dummy Pattern Insertion Quality Examination Method
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Solution Overview
Problem
Existing dummy pattern insertion programs in semiconductor and integrated circuit layout design often generate unsuitable patterns due to insufficient quality examination, leading to issues like metal residuals and performance inconsistencies, as they may not adequately comply with design rules and pattern density requirements.
Innovation Solution
A method and device that utilize a dummy pattern insertion program to generate and examine circuit layouts, checking compliance with circuit layout design rules, dummy pattern check rules, and pattern density rules through multiple iterations, ensuring that dummy patterns are correctly inserted and do not violate design or density rules, using a relation-check circuit layout with specific layer configurations and distances to prevent unwanted contact and electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy pattern insertion program is used to generate dummy patterns in circuit layout design, then pattern density distribution and device performance uniformity are optimized, but unsuitable dummy patterns may be generated that cause metal residual and device performance inconsistency
Solution Approach 1:
The patent applies preliminary action by performing comprehensive quality examination of the dummy pattern insertion program before actual use. Multiple examination processes are executed in advance to identify and correct potential issues with dummy pattern generation, preventing metal residual and performance inconsistency before they occur in manufacturing.
Solution Approach 2:
The patent implements feedback mechanisms through iterative examination processes where examination results are used to adjust and improve the dummy pattern insertion program. The system continuously refines the program based on examination feedback to ensure generated dummy patterns meet quality standards and do not cause manufacturing defects.
2Productivity
If a sample layout is used for examining dummy pattern insertion program quality, then the examination process can be performed, but the sample layout may not include sufficient reference layers to comprehensively check dummy pattern design
Solution Approach 1:
The patent applies segmentation by dividing the examination process into multiple independent examination processes, each focusing on specific aspects of dummy pattern compliance. Different examination modules check different rule sets (design rules, dummy pattern check rules, pattern density rules) separately, allowing comprehensive coverage without requiring a single complex sample layout with all possible reference layers.
Solution Approach 2:
The patent implements universality by creating examination processes that can handle multiple types of rule checks and layout configurations. The examination system is designed to be multi-functional, capable of examining dummy patterns against various rule sets using different examination methods, making the examination process adaptable to different layout types without requiring specialized reference layers for each case.
3Reliability
If design rule check is performed on dummy-inserted layout, then compliance with design rules can be verified, but comprehensive quality examination of dummy patterns may not be sufficient to prevent manufacturing defects
Solution Approach 1:
The patent segments the quality examination into three distinct examination processes: design rule check, dummy pattern check rule examination, and pattern density rule examination. Each examination type focuses on specific aspects of dummy pattern quality, providing comprehensive coverage without overwhelming complexity in a single examination process.
Solution Approach 2:
The patent adds another dimension to the examination process by introducing multiple examination dimensions (design rules, dummy pattern check rules, pattern density rules) rather than relying on a single examination approach. This multi-dimensional examination strategy comprehensively validates dummy pattern quality from different perspectives, ensuring manufacturing defect prevention.
Data Source
AI summary
A method for examining quality of a dummy pattern insertion program may be implemented using a device that includes hardware. The method may include using the dummy pattern insertion program to generate a dummy-based circuit layout, a first dummy-inserted circuit layout, and a second dummy-inserted circuit layout. The method may further include determining whether the dummy-based circuit layout complies with a set of circuit layout design rules. The method may further include checking whether the first dummy-inserted circuit layout complies with at least one of a set of dummy pattern check rules and a set of pattern density rules. The method may further include examining whether the second dummy-inserted circuit layout complies with at least one of the set of circuit layout design rules, the set of dummy pattern check rules, and the set of pattern density rules.