Dummy Pattern Layout for Intra-Die Resistance Variation Control
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Solution Overview
Problem
Intra-die variation in integrated circuits, particularly resistance variation in conductive patterns, is challenging to control due to factors like wafer-level position dependence and process variations such as rapid thermal annealing, leading to performance inconsistencies across devices on the same chip.
Innovation Solution
A modified pattern layout design is implemented by adding a dummy pattern layout region outside the device region on the same mask, which helps in tuning thermal reflectivity and reducing resistance variations by creating dummy polycrystalline silicon patterns outside the device region during the deposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rapid thermal annealing (RTA) process is used to anneal materials at high ramp rate for short period, then manufacturing efficiency is improved, but intra-die resistance variation increases
Solution Approach 1:
The patent introduces dummy patterns in specific regions (dummy pattern regions) around the device region to locally adjust the pattern density. This creates non-uniform distribution of conductive and insulating materials in targeted areas, compensating for the non-uniform thermal reflectivity caused by RTA processing. The dummy patterns are strategically placed to balance the thermal environment locally, thereby reducing intra-die resistance variation while maintaining high-speed RTA processing.
2Reliability
If pattern density is increased to improve device performance, then device functionality is improved, but thermal reflectivity non-uniformity increases leading to resistance variation
Solution Approach 1:
The dummy patterns act as intermediary elements between the device region and the surrounding areas. These dummy patterns mediate the thermal environment by adjusting the local pattern density, thereby controlling the thermal reflectivity during RTA processing. The dummy patterns are not part of the functional device but serve as intermediaries to create a more uniform thermal field, reducing resistance variation in the actual device regions.
3Area of stationary object
If conventional layout design is used without dummy patterns, then device region area is maximized, but intra-die resistance variation increases
Solution Approach 1:
The patent applies partial action by introducing dummy patterns only in specific regions (dummy pattern regions) rather than uniformly across the entire wafer. This selective placement of dummy patterns allows the majority of the device region to maintain high density for functionality, while局部 areas with dummy patterns compensate for thermal non-uniformity. The dummy patterns are placed strategically where needed to control resistance variation without unnecessarily reducing the overall device region area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes intra-die resistance variation, ensuring uniformity in device performance across the chip by balancing the conductive material/insulating material ratio and adjusting thermal reflectivity, thereby reducing uncertainties in supply voltages and timing accuracy.
Implementation Method 1
the resistance variation of doped polycrystalline silicon patterns on the same chip has a correlation with the pattern density (i.e., area of polycrystalline silicon patter per unit area), which is primarily due to the difference of reflectance of incident RTA lamp spectrum
Implementation Method 2
rapid thermal annealing (RTA) process widely used for annealing materials at a high ramp rate and for a short period of time
Implementation Method 3
depositing a conductive layer on the first dielectric layer; patterning the conductive layer on the first dielectric layer to create at least one device region and at least one dummy pattern region
Data Source
AI summary
Disclosed is a method for fabricating a semiconductor device with intra-die variation control. In one embodiment, a method for fabricating a semiconductor device includes: depositing a first dielectric layer on a semiconductor substrate die; patterning a conductive layer on the first dielectric layer to create at least one device region and at least one dummy pattern region, wherein the at least one device region comprises a plurality of first conductive patterns and the at least one dummy pattern region comprises a plurality of second conductive patterns to control intra-die variation.