Dummy Pattern for NAND Flash Spacer Patterning
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Solution Overview
Problem
Conventional methods for forming semiconductor device patterns, particularly in high-density flash memory devices, face challenges in achieving uniform critical dimensions and depth of focus due to asymmetrical spacer patterns and surface tension effects during the patterning process, leading to distorted profiles and reduced integration density.
Innovation Solution
A simplified spacer patterning method is introduced, where a dummy pattern is formed over the peripheral circuit region during the photoresist pattern formation in the cell region, ensuring uniform capillary force application and preventing edge photoresist pattern bending, thereby maintaining consistent critical dimensions and expanding the depth of focus margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a photoresist pattern is formed only over the cell region, then the manufacturing process is simple, but the edge photoresist pattern bends due to surface tension effects, causing critical dimension differences
Solution Approach 1:
The patent applies different patterning configurations to different regions: the cell region receives the primary photoresist pattern for device formation, while the peripheral circuit region receives a dummy pattern. This local differentiation ensures that edge photoresist patterns in the cell region have adjacent dummy structures providing capillary force support, preventing bending while maintaining overall process simplicity.
Solution Approach 2:
The dummy pattern is formed simultaneously with the photoresist pattern in a preliminary co-patterning step before any etching or spacer formation occurs. This preliminary action ensures that the dummy structures are already in place to provide capillary force support during subsequent processing, preventing edge pattern bending before it can occur.
2Ease of manufacture
If the spacer pattern has an asymmetrical structure, then it can be used as an etching mask, but it is difficult to adjust the critical dimension of the lower underlying layer
Solution Approach 1:
The patent controls the critical dimension of the photoresist pattern through exposure and development parameters, ensuring uniform CD across both cell and peripheral regions. The dummy pattern is designed with specific width parameters (at least twice the photoresist pattern width) to provide adequate capillary force support while maintaining the desired asymmetrical spacer structure for etching mask functionality.
3Productivity
If the critical dimension is reduced below 40 nm, then higher integration density is achieved, but the resolution limit of ArF exposer prevents forming the pattern
Solution Approach 1:
The patent transitions from direct single-patterning to a dimensionally extended approach by forming both photoresist and dummy patterns simultaneously in the planar dimension, then utilizing the vertical dimension through spacer formation. This spacer patterning technique effectively doubles the pattern density while maintaining manufacturable critical dimensions through the self-aligned spacer deposition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable semiconductor device patterns with reduced critical dimension differences and improved depth of focus, enhancing the uniformity and integrity of the semiconductor device profiles.
Implementation Method 1
forming a mask film and a first photoresist film over an underlying layer of a substrate that includes a cell region and a peripheral circuit region; first patterning the first photoresist film to form a first photoresist pattern over the cell region and a dummy pattern over the peripheral circuit region
Implementation Method 2
forming a spacer at sidewalls of the first photoresist pattern and the dummy pattern
Implementation Method 3
removing the first photoresist pattern and the dummy pattern to form a spacer pattern over the cell region
Data Source
AI summary
A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.