Semiconductor Package Dummy Pattern Layout for Pad Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The external pads of a substrate in semiconductor packages are prone to discoloration and oxidation, necessitating surface treatment which limits the formation region of interconnection lines due to the removal of plating lines, restricting design freedom.
Innovation Solution
A semiconductor package design featuring first and second dummy patterns with specific through-holes and cut surfaces, allowing for increased spacing and reduced interference, thereby enhancing the design freedom of interconnection patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plating lines are removed to electrically isolate pads after surface treatment, then electrical isolation is improved, but the formation region of interconnection lines is limited
Solution Approach 1:
The substrate surface is divided into multiple regions: pads regions (with second through-holes for electrical connection), etch-back regions (with first through-holes for electrical isolation), and interconnection formation regions (between etch-back regions). This segmentation allows simultaneous achievement of electrical isolation and sufficient interconnection formation space by spatially separating these conflicting requirements.
Solution Approach 2:
Etch-back regions act as intermediary zones between pads and interconnection lines. These regions with first through-holes provide electrical isolation while the spaces between them serve as formation regions for interconnection lines, thus mediating between the need for isolation and the need for interconnection formation space.
2Reliability
If plating lines are removed for electrical isolation, then pad isolation is improved, but design freedom of interconnection patterns is reduced
Solution Approach 1:
By segmenting the substrate into multiple functional regions (pads regions, etch-back regions, interconnection formation regions), the design provides flexibility in arranging interconnection lines within the formation regions while maintaining isolation through etch-back regions. This segmented approach enhances design freedom compared to continuous plating line removal.
Solution Approach 2:
Different regions of the substrate have different properties: pads regions have exposed pads for connection, etch-back regions have through-holes for isolation, and interconnection formation regions have appropriate thickness for line formation. This local differentiation allows optimized design freedom in each region while achieving overall isolation.
3Reliability
If surface treatment is applied to prevent oxidation, then pad protection is improved, but interconnection formation region is limited
Solution Approach 1:
The substrate is segmented into pads regions (with surface treatment and second through-holes) and interconnection formation regions (between first through-holes). This segmentation allows surface treatment to be applied selectively to pads regions for protection while the interconnection formation regions maintain appropriate thickness and properties for line formation.
Solution Approach 2:
Surface treatment is applied locally to pads regions where protection is needed, while etch-back regions and interconnection formation regions have different thickness profiles suitable for their functions. This local quality differentiation resolves the conflict between protection and formation region availability.
Data Source
AI summary
A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.