Dummy Pattern Surface Area Control for Sub-40nm Semiconductor Patterning
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Solution Overview
Problem
Forming patterns narrower than 40 nm is challenging due to limitations in photolithography processes, requiring complex double patterning techniques involving multiple etching processes.
Innovation Solution
A method of manufacturing semiconductor devices that involves forming preliminary main and dummy patterns with controlled upper surface areas, using sacrificial layers and spacers as etching masks, and subsequent planarization with CMP to achieve precise pattern formation and reduce etching complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning is used to form patterns narrower than 40 nm, then pattern precision is improved, but device complexity increases due to multiple etching processes
Solution Approach 1:
The patent applies preliminary action by forming dummy patterns before the main patterning process. These dummy patterns are created in advance to establish reference levels and guide subsequent etching operations, enabling precise formation of sub-40nm patterns while simplifying the overall process flow by pre-defining critical dimensions
Solution Approach 2:
The patent uses dummy patterns as intermediary elements that mediate between the photolithography process and the final pattern formation. These intermediary structures serve as etching masks and reference features that enable precise main pattern formation without requiring complex multi-step etching sequences
2Manufacturing precision
If multiple etching processes are used for double patterning, then pattern precision is improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple etching operations into a streamlined process by using dummy patterns that serve multiple functions simultaneously - as etching masks, reference features, and process control elements. This consolidation reduces the number of separate etching steps required while maintaining sub-40nm pattern precision
3Manufacturing precision
If dummy patterns are formed with full area coverage, then planarization quality is improved, but material consumption increases
Solution Approach 1:
The patent applies local quality by forming dummy patterns with selective area coverage rather than uniform full coverage. The dummy patterns are strategically positioned to provide sufficient planarization reference surfaces in critical areas while minimizing material consumption in non-critical regions, optimizing the balance between planarization quality and material efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of patterns with widths less than 40 nm by simplifying the etching process and improving pattern precision and defect reduction, while also serving as a polish stop layer for planarization.
Implementation Method 1
planarization is performed on the dummy pattern region
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.