Dummy Patterns for CMP Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional dummy patterns with identical shapes and sizes are inadequate for wafer planarization, especially in complex integrated circuit designs, leading to uneven surfaces, pattern size errors, and increased optical proximity correction processing time due to varying pattern densities.
Innovation Solution
A method for generating dummy patterns by inserting first, second, and third dummy patterns with varying sizes and densities, adjusting their sizes based on sub-region densities to equalize pattern densities, and outputting them on a photomask for improved chemical mechanical polishing (CMP) results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional dummy patterns with identical shapes and sizes are used, then the pattern density is raised in low density regions, but the wafer surface remains uneven and CMP results deteriorate due to complex IC design variations
Solution Approach 1:
The patent applies local quality by varying the size and density of dummy patterns according to the specific requirements of different sub-regions. Instead of using uniform dummy patterns throughout, the method calculates and implements region-specific dummy pattern configurations that match the local density variations caused by complex IC designs, thereby achieving uniform CMP results across the entire wafer surface.
Solution Approach 2:
The patent segments the wafer surface into multiple sub-regions and processes each region independently with customized dummy patterns. This segmentation allows the method to address local density variations in different areas of the wafer, preventing the uniform dummy pattern approach from failing in complex IC designs with varying pattern densities across different regions.
2Manufacturing precision
If dummy patterns are inserted to equalize pattern density, then CMP results improve, but optical proximity correction (OPC) processing time increases
Solution Approach 1:
The patent applies preliminary action by inserting dummy patterns before the OPC process to equalize pattern densities across the wafer. By pre-balancing the density distribution, the subsequent OPC process encounters more uniform conditions, which reduces the computational complexity and processing time required for OPC while maintaining high CMP result quality.
3Manufacturing precision
If dummy patterns are used in low pattern density regions, then material etching uniformity improves, but pattern size error and critical size uniformity deteriorate due to stress between regions with different pattern densities
Solution Approach 1:
The patent applies local quality by creating sub-regions with customized dummy pattern densities that match the local characteristics. This approach gradually transitions between different density regions rather than creating sharp boundaries, thereby reducing stress between regions with different pattern densities while maintaining etching uniformity and improving critical size uniformity.
Data Source
AI summary
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns.