Dummy Pixel Circuit Layout for Through-Via Display Mura
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Solution Overview
Problem
Display panels with through vias experience reduced luminance due to the load on gate lines, leading to display mura issues, as the gate voltage is lower than the source voltage, resulting in less current flow through the drive transistor.
Innovation Solution
A dummy pixel circuit is introduced between two through vias, connected to a gate line with a bend, comprising transistors that increase the total load on the gate line, reducing the storage capacity of the capacitor and increasing the gate voltage, thereby enhancing luminance by increasing current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through vias are added for camera and earpiece placement, then device functionality is improved, but pixel circuit luminance deteriorates due to increased load and decreased gate voltage
Solution Approach 1:
A dummy pixel circuit is introduced as an intermediary element between the through vias and the actual pixel circuits. This dummy circuit absorbs excess power and regulates the electrical load, preventing the gate voltage drop that would otherwise occur due to the additional through vias. The dummy circuit acts as a buffer that mediates between the structural modifications and the functional requirements of the display.
Solution Approach 2:
The invention modifies the electrical parameters of the pixel circuit by adding a dummy circuit with specific power consumption characteristics. This changes the overall load distribution and power dynamics in the display panel, thereby maintaining gate voltage within acceptable ranges despite the presence of additional through vias for camera and earpiece functionality.
2Adaptability or versatility
If through vias are added for camera and earpiece placement, then device functionality is improved, but display uniformity deteriorates due to display mura
Solution Approach 1:
The dummy pixel circuit serves as an intermediary that balances the electrical load across different regions of the display. By strategically placing dummy circuits near through vias, the invention compensates for local variations in power consumption and voltage distribution, thereby maintaining overall display uniformity despite the structural disruptions caused by through vias.
Solution Approach 2:
The dummy pixel circuit performs a preliminary compensatory action by pre-balancing the electrical load before it reaches the actual pixel circuits. This preemptive measure counteracts the potential negative effects of through vias on display uniformity, preventing display mura from occurring in the first place.
3Adaptability or versatility
If gate line length is increased to bypass through vias, then device functionality is maintained, but gate voltage deteriorates due to increased resistance
Solution Approach 1:
The invention changes the power distribution parameters by introducing dummy pixel circuits that locally regulate voltage and power consumption. This compensates for the voltage drop caused by longer gate lines, maintaining gate voltage within acceptable ranges despite the increased path length required to bypass through vias.
Data Source
AI summary
The present disclosure relates to a dummy pixel circuit, a display panel, and a display device, which belongs to the field of display. The dummy pixel circuit is applicable to a display panel provided with two through vias and disposed between the two through vias, and the dummy pixel circuit includes a pixel sub-circuit and a dummy sub-circuit. The pixel sub-circuit includes one or more first transistors, wherein a control electrode of the first transistor is electrically connected to the first gate line. The dummy sub-circuit includes one or more second transistors, wherein a control electrode of the dummy sub-circuit is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor. Each of the one or more first transistors corresponds to at least one of the one or more second transistors. The second transistor consumes the power transmitted transferred by the first gate line, and thus a total load of the pixel circuit electrically connected to the first gate line is increased. In this way, the pixel, to which the pixel circuit electrically connected to the first gate line corresponds, has an increased luminance, thereby mitigating display mura of display panel.