Dummy Poly Pattern Insertion for CMP Border Planarization
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Solution Overview
Problem
Chemical mechanical polishing (CMP) dishing effect leads to nonplanar surfaces and under-polish defects in semiconductor fabrication, particularly in small border regions between IP blocks, causing reliability issues and production losses due to the mismatch in gate metal layer thickness and under-polish defects.
Innovation Solution
Insertion of small dummy POLY patterns in small border regions with dimensions between 0.5 μm and 3.6 μm, which mitigates the CMP dishing effect by introducing a heterogeneous material distribution, ensuring a flat top surface post-CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is performed on semiconductor wafers, then the gate metal layer is polished to achieve planarization, but the CMP dishing effect causes nonplanar surfaces and under-polish defects in small border regions
Solution Approach 1:
The patent applies preliminary action by inserting dummy gate patterns into small border regions before the CMP process. These dummy patterns are strategically placed in advance to modify the material distribution and polishing characteristics in border regions, preventing under-polish defects from occurring during the subsequent CMP process.
Solution Approach 2:
The patent applies local quality by creating heterogeneous material distribution specifically in small border regions through dummy gate pattern insertion. This local modification changes the polishing behavior only in the problematic border areas while leaving the main IP blocks unchanged, achieving selective planarization control where it is most needed.
2Reliability
If dummy gate patterns are inserted in small border regions, then under-polish defects are reduced, but the device structure becomes more complex
Solution Approach 1:
The patent applies this principle by using simple, inexpensive dummy gate patterns that serve a temporary purpose during manufacturing. These dummy patterns are basic geometric structures inserted solely for process control during CMP, and they can be removed or overwritten in subsequent processing steps, providing a low-cost solution to a complex problem.
Solution Approach 2:
The patent applies parameter changes by modifying the material distribution parameters in border regions through dummy gate insertion. This changes the local polishing parameters and material heterogeneity in a controlled manner, achieving defect reduction through parameter optimization rather than fundamental design changes.
3Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but the CMP dishing effect becomes more pronounced in small border regions
Solution Approach 1:
The patent applies local quality by targeting only the small border regions for dummy gate pattern insertion, leaving the main IP blocks with high integration density unchanged. This localized approach maintains the high productivity benefits of reduced feature size in the functional areas while separately addressing the CMP planarization quality issue in the border regions.
Solution Approach 2:
The patent applies preliminary action by proactively inserting dummy gates in border regions before CMP processing, anticipating and preventing the dishing effect that becomes more pronounced at smaller feature sizes. This preliminary modification allows continued scaling for higher integration density while maintaining planarization quality.
Data Source
AI summary
A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.