On-Grid Dummy Poly Layout for Dense IC Isolation Regions
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Solution Overview
Problem
Integrated circuit layouts face challenges in optimizing space utilization due to design rules that require significant spacing between active and dummy device structures, leading to inefficiencies in chip area usage, particularly at the 5 nm technology node.
Innovation Solution
The method involves generating an integrated circuit layout with a first array of linear features over an active device area and inserting a second array of linear features as dummy fill, which are on the same grid as the first array, allowing the dummy fill to be closer to the active device area, thereby improving anti-dishing performance and reducing empty space. This is achieved by forming a continuous array of poly lines on the semiconductor substrate, with the dummy device structure extending over a substantial portion of the distance between active device areas, using double patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If minimum spacing is required between active device structure and dummy device structure, then proper spacing for electrical isolation and manufacturability is ensured, but chip area is consumed significantly
Solution Approach 1:
The patent introduces a graded doping profile as an intermediary mechanism between the active device structure and dummy device structure. This graded doping region provides gradual electrical isolation, allowing the dummy structure to be placed closer to the active structure while still maintaining proper electrical isolation and manufacturability
Solution Approach 2:
The patent changes the doping parameter from uniform to graded profile in the region between active and dummy structures. By varying the doping concentration gradually, the electrical isolation is maintained while reducing the spacing requirement, thus optimizing chip area utilization
2Area of stationary object
If dummy device structure is placed closer to active device area, then empty space is reduced and density improved, but anti-dishing performance may be compromised
Solution Approach 1:
The patent modifies the doping concentration parameter in the region between active and dummy structures. By implementing a graded doping profile with varying concentration, the structure maintains sufficient mechanical support for anti-dishing performance while allowing closer placement to reduce empty space
3Area of stationary object
If larger portion of space between active device areas is occupied by dummy device structure, then chip area usage is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs a graded doping profile that can be implemented through controlled diffusion or ion implantation processes. While the doping profile is complex, the overall manufacturing process remains compatible with standard semiconductor fabrication techniques, balancing area optimization with manufacturing feasibility
Data Source
AI summary
An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.