Dummy Polysilicon Lines for SRAM Sense Amplifier Matching
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Solution Overview
Problem
Sense amplifiers in SRAM memory circuits are prone to failure due to mismatches between inverters caused by process and operation variations, leading to incorrect logic state reporting.
Innovation Solution
A multiple finger structure for NMOS transistors is implemented, with symmetric layout and overlapping dummy polysilicon lines to minimize parameter shifts and ensure matching performance across transistors, forming a robust positive feedback system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional layout of inverters is used in sense amplifiers, then the device complexity is low, but mismatch between inverters occurs due to process and operation variations, leading to sense amplifier failure
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy polysilicon lines adjacent to the first inverter that are not present next to the second inverter. This asymmetric structure compensates for process variations by creating matched parameter shifts in the NMOS transistors of both inverters, thereby improving sense amplifier reliability without requiring complete symmetry in the physical layout
Solution Approach 2:
The patent implements local quality by modifying only specific regions of the inverter layout - adding dummy polysilicon lines locally next to the first inverter's NMOS transistors. This localized modification addresses the mismatch problem without redesigning the entire sense amplifier structure, maintaining overall device simplicity while improving reliability
2Manufacturing precision
If process variations are reduced to minimize mismatch, then the manufacturing precision increases, but the manufacturing cost and complexity increase
Solution Approach 1:
The patent changes the physical parameters of the inverter structure by adding dummy polysilicon lines that alter the local electric field distribution and transistor characteristics. This parameter modification approach achieves better effective matching without requiring tighter process control, thereby maintaining ease of manufacture while improving transistor parameter matching
Solution Approach 2:
The dummy polysilicon lines act as intermediary elements that mediate the effect of process variations on the NMOS transistors. By introducing these intermediate structures, the patent compensates for manufacturing variations without needing to improve the fundamental manufacturing precision, keeping the fabrication process simple
Data Source
AI summary
A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.