Dummy Pull-Down Transistor for Gate Driving Circuit Current Sensing
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Solution Overview
Problem
Current display devices face challenges in reducing the size of the non-display area, which limits design freedom and increases the complexity and defect rate of gate driving circuits, while also affecting the lifetime of transistors.
Innovation Solution
A gate driving circuit is designed with a reduced number of transistors, incorporating a pull-up transistor, a pull-down transistor, and a dummy pull-down transistor to control the gate signal, along with a control circuit that adjusts the stress on the transistors, allowing for a narrower bezel and extended transistor lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the non-display area size is reduced, then design freedom and design quality are improved, but the complexity and defect rate of gate driving circuits increase
Solution Approach 1:
The patent extracts the sensing function from the main gate driving circuit by introducing a separate dummy pull-down transistor. This dummy transistor is dedicated solely to sensing current, while the main pull-down transistor handles the primary switching function. This separation removes the sensing complexity from the main circuit, allowing the gate driving circuit to be simplified and reduced in size.
Solution Approach 2:
The dummy pull-down transistor acts as an intermediary element that mediates between the main circuit and the sensing requirements. By using this intermediate component, the patent enables current sensing without requiring complex circuitry in the main gate driving path, thus reducing overall circuit complexity while maintaining the ability to monitor and protect against overcurrent conditions.
2Adaptability or versatility
If more circuit elements are arranged in the non-display area, then functionality is improved, but the size reduction becomes more difficult
Solution Approach 1:
The dummy pull-down transistor serves multiple functions: it acts as a sensing element for current monitoring, provides a path for stress testing to extend transistor lifetime, and enables defect detection. By consolidating these multiple functions into a single dedicated component rather than requiring separate circuit elements, the patent reduces the overall area required in the non-display region while maintaining enhanced functionality.
Solution Approach 2:
The patent merges the sensing function with the existing pull-down transistor structure by adding a dummy parallel transistor rather than introducing completely separate sensing circuitry. This merging approach allows current sensing capabilities to be integrated into the gate driving circuit without requiring additional independent components, thereby reducing the total area occupied in the non-display region.
3Speed
If transistor stress is increased to improve performance, then switching speed is improved, but transistor lifetime is reduced
Solution Approach 1:
The dummy pull-down transistor is configured to experience the same stress conditions as the main pull-down transistor during normal operation. By subjecting the dummy transistor to identical stress, the patent enables preliminary testing and monitoring of transistor degradation. This allows for predictive maintenance and optimization of stress levels to balance performance and lifetime requirements.
Solution Approach 2:
The dummy pull-down transistor provides feedback information about the actual stress experienced by the main transistor through current sensing. By monitoring the current through the dummy transistor, the system can detect signs of transistor degradation and adjust operating conditions to prevent excessive stress, thereby extending transistor lifetime while maintaining optimal performance.
Data Source
AI summary
A display device is provided that includes a display panel including one or more sub-pixels and a gate driving circuit supplying a gate signal to the sub-pixels through gate lines, the gate driving circuit including a gate output buffer circuit including a pull-up transistor that controls a connection between a clock input node and a gate output node, and a pull-down transistor that controls a connection between a low level voltage node and the gate output node, a control circuit capable of controlling the gate output buffer circuit, and a dummy pull-down transistor whose a gate node is shared with a gate node of the pull-down transistor.