Dummy Ring Array Boundary Structure for CMP Dishing Control
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Solution Overview
Problem
The integration of Non-Volatile Memory (NVM) cell arrays in advanced CMOS processes for smart cards and automotive applications faces a dishing issue during Chemical Mechanical Polishing (CMP) due to the gate height difference between NVM cell arrays and logic devices, leading to fabrication challenges.
Innovation Solution
A method involving the formation of a semiconductor structure with a dummy ring structure, where a dielectric layer with varying thickness portions is used to cover the trench isolations and semiconductor portion, effectively reducing the gate height difference and mitigating CMP dishing by creating a planarized surface during polishing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate height of NVM cell array is made higher than periphery circuit to achieve proper device functionality, then the NVM cell array can operate correctly with sufficient gate control, but CMP dishing occurs during polishing processes affecting manufacturing precision
Solution Approach 1:
A dummy ring structure is formed around the NVM cell array before CMP processing. This dummy ring has a height that is higher than the NVM cell array gate, creating a preliminary height profile that prevents dishing during subsequent CMP processes by providing a buffer zone that absorbs the polishing pressure.
Solution Approach 2:
The dummy ring acts as an intermediary structure between the high gate NVM cell array and the lower gate periphery circuit. It mediates the height difference by providing a transition zone that protects the NVM cell array from direct CMP dishing while maintaining the necessary gate height for device operation.
2Productivity
If standard CMP processes are used to polish the wafer surface, then manufacturing efficiency is maintained, but dishing expands into sensitive regions causing yield loss
Solution Approach 1:
The dummy ring structure is prepared in advance before CMP processing, creating a protective barrier that allows standard CMP processes to be used without modification while preventing dishing from expanding into the sensitive NVM cell array regions during polishing.
Solution Approach 2:
The dummy ring converts the potentially harmful effect of CMP dishing into a beneficial protective mechanism. By positioning the dummy ring with higher height around the NVM cell array, the dishing that would normally occur during CMP is redirected to affect the dummy ring instead, thereby protecting the sensitive regions and improving yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield rate of memory cell arrays by preventing CMP dishing from expanding into sensitive regions, thus protecting the memory cell array and maintaining the integrity of the semiconductor structure during polishing processes.
Implementation Method 1
The gate height difference between the embedded NVM cell array and the logic devices results in dishing issue during the successive Chemical Mechanical Polishing (CMP) processes.
Data Source
AI summary
A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.