TSV Dummy Section Placement for Notch-Free Via Sidewalls
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Solution Overview
Problem
The formation of notches in the sidewall of Through Silicon VIA holes during the dry etching process in semiconductor devices leads to insufficient barrier metal coverage, causing copper diffusion into the substrate and reliability issues in semiconductor devices with Through Silicon VIA electrodes.
Innovation Solution
A dummy pattern is formed in the non-active area to prevent the outer edge of the Through Silicon VIA electrode from intersecting with the boundary between the insulating region and the dummy section, thereby avoiding the scattering of etching ions and ensuring complete barrier metal coverage on the sidewall of the VIA hole.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If Through Silicon VIA holes are formed in the non-active area with dummy actives to prevent dishing, then dishing prevention is achieved, but notches are generated in the sidewall of the Through Silicon VIA holes
Solution Approach 1:
The dummy actives are formed in advance during the STI formation process, before the Through Silicon VIA holes are etched. This preliminary placement of dummy actives in the non-active area creates a more uniform polishing surface that prevents dishing during CMP, while the careful design of dummy active placement avoids intersecting with Through Silicon VIA hole boundaries, thus preventing notch formation.
Solution Approach 2:
Dummy actives are selectively placed only in the non-active area where STI regions exist and dishing is likely to occur, rather than uniformly across the entire substrate. This localized approach prevents dishing in critical areas while avoiding interference with Through Silicon VIA hole formation in active regions, thereby maintaining sidewall quality.
2Ease of manufacture
If the outer edge of Through Silicon VIA electrode intersects with the boundary between insulating region and dummy section, then etching ions are scattered, but notches are generated in the sidewall
Solution Approach 1:
The dummy actives are designed with asymmetric placement relative to the Through Silicon VIA holes, specifically positioned away from the hole boundaries. This asymmetric arrangement ensures that the outer edge of Through Silicon VIA electrodes does not intersect with the boundary between insulating regions and dummy sections, preventing etching ion scattering and subsequent notch formation while still maintaining dishing prevention in the STI areas.
3Reliability
If barrier metal coverage is insufficient due to notches, then copper diffusion occurs into the substrate, but device reliability deteriorates
Solution Approach 1:
By carefully designing the dummy active placement to avoid intersecting with Through Silicon VIA hole boundaries, the invention prevents the formation of notches before they can occur. This preliminary preventive measure ensures that the barrier metal can be deposited with complete coverage on the sidewalls of Through Silicon VIA holes, maintaining its function as an effective diffusion barrier against copper and ensuring device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the generation of notches in the sidewall of the Through Silicon VIA holes, allowing for reliable formation of the barrier metal and preventing copper diffusion into the semiconductor substrate, thereby enhancing the quality, reliability, and stability of the semiconductor device.
Implementation Method 1
A dry etching step for forming Through Silicon VIA holes in the non-active area in which the plurality of dummy actives is formed is included in the steps for manufacturing an image sensor
Implementation Method 2
there is a problem in that notches (outwardly expanding depressions in the side wall of the Through Silicon VIA hole) are generated in the sidewall of the Through Silicon VIA holes when Through Silicon VIA holes are formed so as to pass through the non-active area in which the plurality of dummy actives is uniformly disposed
Implementation Method 3
insufficient barrier metal coverage, causing copper diffusion into the substrate and reliability issues in semiconductor devices with Through Silicon VIA electrodes
Data Source
AI summary
There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.