Dummy Solder Structure for IC Corner Delamination Prevention
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Solution Overview
Problem
Integrated circuit (IC) packages, particularly flip chip ball grid array (FC-BGA) packages, face reliability issues due to delamination between the IC chip and underfill at the chip's corners, caused by stress from different thermal expansion coefficients and reduced adhesion, leading to interconnect solder bump cracking and electrical failures.
Innovation Solution
Incorporating dummy solder structures directly under the corners of the IC chip package, which are larger in volume than the interconnect solder structures, to prevent underfill from forming and thus eliminate chip-underfill delamination, without violating dicing rules by being metal pads during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy interconnect solder bumps are added near the corners of the IC chip to prevent delamination, then reliability is improved, but dicing rules are violated and interconnect solder bumps may be removed during dicing
Solution Approach 1:
The invention extracts the dummy solder bump placement from the chip corner area and relocates it to the substrate side, specifically at mounting metal pads positioned at the corners of the substrate. This separation allows the dummy structures to fulfill their stress-distribution function without interfering with the dicing process of the IC chip.
Solution Approach 2:
The invention introduces mounting metal pads as intermediary structures on the substrate that serve as anchor points for dummy solder bumps. These mounting metal pads act as mediators between the substrate and the dummy solder bumps, enabling the dummy structures to be placed optimally for stress distribution while maintaining compatibility with the dicing process.
2Reliability
If interconnect solder bumps are placed on the IC chip before dicing to provide electrical connections, then electrical connectivity is achieved, but dicing rules are violated and some interconnect solder bumps may be removed
Solution Approach 1:
The invention extracts the dummy solder bump functions from the chip corner region and relocates them to the substrate side, where they can be placed on mounting metal pads without violating dicing rules. This spatial separation preserves both the electrical connection integrity and dicing process compliance.
Solution Approach 2:
The invention moves the dummy solder bump placement from the horizontal plane of the chip surface to the vertical stacking sequence, placing them on the substrate side after the chip is diced. This dimensional repositioning allows the dummy structures to fulfill their stress-distribution function without interfering with the dicing process.
3Reliability
If underfill is applied to stabilize interconnections and seal from moisture, then adhesion and sealing are improved, but delamination occurs at chip corners due to thermal expansion stress
Solution Approach 1:
The invention introduces dummy solder bumps as counterbalancing structures that distribute and counteract the thermal expansion stress concentrated at the chip corners. These dummy structures act as stress-absorbing elements that compensate for the harmful stress effects, preventing delamination while preserving the beneficial adhesion and sealing properties of the underfill.
Solution Approach 2:
The invention applies dummy solder bumps specifically at the corner regions where thermal expansion stress is most concentrated, rather than uniformly across the entire chip. This localized application addresses the specific problem area while maintaining the overall integrity and function of the underfill material in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy solder structures effectively prevent underfill delamination at the chip's corners, enhancing the reliability of the IC package by distributing stress and maintaining the integrity of interconnect solder bumps during the dicing process.
Implementation Method 1
an interconnect solder structure electrically connecting each of the first and second plurality of interconnect metal pads
Implementation Method 2
Delamination can also be caused by high stress at a lower temperature side of the IC chip from different coefficients of thermal expansion of materials
Implementation Method 3
The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures
Implementation Method 4
The FC-BGA packages have an UF material, usually an epoxy, or acrylic and silicone material, inserted about the C4s to stabilize the interconnections, seal the interconnections from moisture
Data Source
AI summary
An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.