Dummy Spacer Layer for Vertical FET Junction Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing techniques fail to create optimal bottom source-drain junction profiles for both thick-oxide and thin-oxide devices on the same substrate, leading to inadequate dopant diffusion and performance degradation in vertical transistors.
Innovation Solution
A method involving the formation of a dummy spacer layer with dopants on the bottom source/drain region in thick-oxide devices, which extends dopant diffusion to greater heights along the fins, ensuring that the source-drain junction profiles penetrate sufficiently to match the vertical height of thicker gate oxides, while maintaining optimal junction formation for thin-oxide devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single bottom source-drain junction profile is used for both thick-oxide and thin-oxide devices, then manufacturing process is simplified, but device performance degrades due to inadequate dopant diffusion for thick-oxide devices
Solution Approach 1:
The patent introduces a dummy spacer layer selectively in thick-oxide device regions to create locally different dopant diffusion conditions. This allows the bottom source-drain junction in thick-oxide regions to achieve sufficient dopant penetration depth while thin-oxide regions maintain their original junction profile, thus resolving the contradiction between manufacturing simplicity and device performance
Solution Approach 2:
The dummy spacer layer acts as an intermediary element that facilitates enhanced dopant diffusion in thick-oxide regions. By introducing this intermediate structure, the patent enables differentiated junction formation without requiring completely separate manufacturing processes for thick-oxide and thin-oxide devices
2Manufacturing precision
If dopant diffusion is extended to greater heights in thick-oxide devices, then junction profile penetrates sufficiently to match gate oxide thickness, but manufacturing complexity increases due to dummy spacer layer formation
Solution Approach 1:
The dummy spacer layer is formed preliminarily before the dopant diffusion process in thick-oxide regions. This preliminary structure enables controlled dopant diffusion to greater heights, ensuring precise junction profile formation that matches the thicker gate oxide while adding minimal process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that both thick-oxide and thin-oxide devices achieve optimized source-drain junction profiles, enhancing performance by ensuring sufficient dopant penetration and matching junction heights to gate structures, thereby addressing the limitations of existing methods.
Implementation Method 1
forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants, and forming a plurality of doped regions in the first and second plurality of fins
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first plurality of fins in a first device region on a substrate, forming a second plurality of fins in a second device region on the substrate, forming bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of fins in the first and second device regions, forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants, and forming a plurality of doped regions in the first and second plurality of fins in the first and second device regions, wherein the plurality of doped regions in the first device region extend to a greater height on the first plurality of fins than the plurality of doped regions in the second device region on the second plurality of fins.