Fish Bone Nanosheet Structure for Overlay-Stable Stack Scaling
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Solution Overview
Problem
The nanosheet device has a larger minimum channel dimension compared to FinFET devices, and aggressive scaling down in semiconductor manufacturing introduces complexity and issues such as constrained patterning windows due to limited distance between adjacent nanosheet stacks.
Innovation Solution
A nanosheet device with a fish bone structure is introduced, featuring a dummy spacer between adjacent same-type semiconductor layer stacks to separate metal gates and epitaxial source/drain features, reducing the distance between stacks and mitigating overlay shifting issues during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanosheet device is used to improve gate control performance, then device performance is improved, but minimum channel dimension becomes much larger than FinFET device
Solution Approach 1:
The channel is segmented into multiple thin nanosheet layers stacked vertically, allowing the gate to control multiple channel segments simultaneously. This segmentation enables better gate control performance while maintaining a compact lateral footprint, effectively resolving the contradiction between improved gate control and reduced channel dimension.
Solution Approach 2:
The invention transitions from a two-dimensional planar channel to a three-dimensional stacked nanosheet structure. By stacking multiple thin channel layers vertically, the device achieves enhanced gate control through increased gate-channel interaction surface area while keeping the lateral channel dimension small, thus resolving the contradiction between gate control performance and channel dimension.
2Area of moving object
If aggressive scaling down is applied to reduce device size, then device compactness is improved, but patterning window becomes constrained due to limited distance between adjacent nanosheet stacks
Solution Approach 1:
The invention moves the scaling challenge from the lateral dimension to the vertical dimension by stacking nanosheets. This allows aggressive lateral scaling to reduce device footprint while maintaining adequate lateral spacing between adjacent stacks for patterning processes, effectively resolving the contradiction between device compactness and manufacturability.
Solution Approach 2:
The channel is segmented into multiple thin nanosheet layers stacked vertically, allowing the gate to control multiple channel segments simultaneously. This segmentation enables better gate control performance while maintaining a compact lateral footprint, effectively resolving the contradiction between improved gate control and reduced channel dimension.
3Area of moving object
If distance between adjacent nanosheet stacks is reduced to improve device compactness, then device size is reduced, but overlay shifting issues increase during fabrication
Solution Approach 1:
Dummy spacers are introduced as intermediary structures between adjacent nanosheet stacks of the same type. These spacers act as physical reference markers that define the spacing between stacks, enabling precise alignment and reducing overlay shifting issues during subsequent lithography processes, thus resolving the contradiction between device compactness and manufacturing precision.
Solution Approach 2:
The dummy spacers are formed in advance before the critical alignment steps. By establishing the spacing between nanosheet stacks with these preliminary spacer structures, the invention provides stable reference features for subsequent patterning operations, reducing overlay shifting and improving manufacturing precision while maintaining compact device dimensions.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.