Dummy SRAM Cell Grounding for Stable Self-Timed Memory Reads
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Solution Overview
Problem
The floating states of nodes in dummy memory cells due to disconnection from bit lines in self-timed memory circuits can adversely affect the accuracy of self-timing operations by causing varying device capacitance and signal coupling, impacting the rise time of word line signals.
Innovation Solution
Implementing direct circuit connections between the source/drain nodes of dummy memory cells and ground nodes, fixing the capacitive load on dummy word lines, ensuring consistent signal propagation times for write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy memory cells are disconnected from bit lines to simplify circuit structure, then device complexity is reduced, but manufacturing precision deteriorates due to varying device capacitance affecting self-timing accuracy
Solution Approach 1:
A ground connection is introduced as an intermediary element between the source/drain nodes of dummy memory cells and the ground node. This mediator provides a fixed reference potential that stabilizes the capacitive load on dummy word lines, ensuring consistent signal propagation times while maintaining the simplified disconnected structure from bit lines.
Solution Approach 2:
The capacitive load parameter of dummy memory cells is controlled and fixed by connecting source/drain nodes to ground. This parameter change ensures that dummy word lines experience consistent capacitive loading, which stabilizes signal rise times and improves self-timing accuracy without increasing overall circuit complexity.
2Object-affected harmful factors
If dummy memory cells are disconnected from bit lines to reduce signal interference, then harmful factors are reduced, but reliability deteriorates due to inconsistent signal propagation times
Solution Approach 1:
The ground connection serves as a stable intermediary that references the potential of disconnected dummy memory cell nodes. This mediator prevents floating node effects and ensures consistent capacitive loading, which stabilizes signal propagation times and improves the reliability of self-timing operations while maintaining isolation from bit line interference.
Solution Approach 2:
By connecting source/drain nodes to ground, the patent establishes equipotential conditions for dummy memory cells during write operations. This ensures that all dummy cells experience the same reference potential, eliminating variations in signal propagation times and improving the reliability of self-timing without requiring connection to active bit lines.
3Measurement precision
If direct ground connections are added to dummy memory cells to stabilize capacitance, then self-timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent controls the capacitive load parameter by adding ground connections to dummy memory cells. This parameter change stabilizes the capacitive environment on dummy word lines, ensuring consistent signal propagation times and improving self-timing accuracy. The added complexity is minimal since ground connections utilize existing circuit infrastructure.
Data Source
Figure 1
Figure 2~3
Figure 4A
AI summary
A dummy SRAM cell included in a dummy row of a memory circuit includes first and second data storage nodes connected by cross-coupled latch circuitry. A first passgate transistor has a first source/drain node directly connected to the first data storage node, a second source/drain node directly connected to a ground node, and a gate node coupled to a dummy word line. The first data storage node is further directly connected to the ground node. A second passgate transistor has a first source/drain node directly connected to the second data storage node, a second source/drain node directly connected to the first source/drain node, and a gate node coupled to the dummy word line. A read transistor and transfer transistor are coupled in series. A gate node of the transfer transistor is coupled to a dummy read word line and a source/drain node of the transfer transistor is directly connected to the ground node.