Dummy SRAM Cell Grounding for Accurate Self-Timed Memory
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Solution Overview
Problem
The floating states of nodes in dummy memory cells due to disconnection from bit lines in self-timed memory circuits can adversely affect the accuracy of self-timing operations, leading to varying signal rise times and inaccurate timing control.
Innovation Solution
Implementing direct circuit connections between the source/drain nodes of dummy memory cells and ground nodes, fixing the capacitive load on dummy word lines, ensuring consistent signal propagation and timing control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy memory cells are disconnected from bit lines to simplify circuit structure, then device complexity is reduced, but manufacturing precision deteriorates due to floating node states affecting self-timing accuracy
Solution Approach 1:
The patent introduces ground nodes as intermediary elements connected to the source/drain nodes of dummy memory cells. These ground connections act as mediators that stabilize the floating nodes without requiring connections to active bit lines, thereby maintaining circuit simplicity while ensuring accurate self-timing operation.
Solution Approach 2:
The patent changes the electrical state parameter of the dummy memory cell nodes from floating (undefined voltage) to grounded (fixed at ground potential). This parameter change stabilizes the capacitive load on dummy word lines and eliminates timing variations caused by floating node voltage fluctuations.
2Ease of operation
If dummy memory cells are disconnected from bit lines to reduce connections, then ease of operation is improved, but reliability deteriorates due to varying signal rise times
Solution Approach 1:
Ground nodes serve as stable intermediary reference points that provide consistent electrical potential to dummy memory cell nodes. This intermediary connection ensures reliable signal propagation timing without requiring complex bit line connections, maintaining ease of operation while improving timing reliability.
Solution Approach 2:
The patent applies equipotentiality by connecting all dummy memory cell source/drain nodes to ground, ensuring they all operate at the same reference potential. This eliminates voltage variations and signal rise time differences, ensuring reliable and consistent timing control across all dummy cells.
3Manufacturing precision
If direct ground connections are added to dummy memory cells to stabilize timing, then self-timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent creates a simplified copy of the memory cell structure for dummy cells that only includes essential ground connections rather than full bit line connections. This copied structure maintains the timing function while reducing complexity by omitting unnecessary connection elements.
Solution Approach 2:
The patent extracts only the essential ground connection function from the full bit line connection system. By taking out just the necessary grounding element and removing unnecessary bit line connections, the solution achieves accurate self-timing while minimizing added complexity.
Data Source
AI summary
A dummy SRAM cell included in a dummy row of a memory circuit includes first and second data storage nodes connected by cross-coupled latch circuitry. A first passgate transistor has a first source/drain node connected to the first data storage node, a second source/drain node connected to a ground node, and a gate node coupled to a dummy word line. The first data storage node is further connected to the ground node. A second passgate transistor has a first source/drain node connected to the second data storage node, a second source/drain node connected to the first source/drain node, and a gate node coupled to the dummy word line. A read transistor and transfer transistor are coupled in series. A gate node of the transfer transistor is coupled to a dummy read word line and a source/drain node of the transfer transistor is connected to the ground node.