Dummy Substrate for 3D IC Warpage Control
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Solution Overview
Problem
Conventional 3D packaging of integrated circuits faces challenges such as asymmetric wafer warpage and surface defects like crystal originated pits due to size differences between integrated circuits, which affect packaging efficiency and quality.
Innovation Solution
The method involves using a dummy substrate with a similar coefficient of thermal expansion to the integrated circuits, arranged to form a rotationally symmetrical shape with the first integrated circuit, to compensate for size differences and ensure proper alignment and encapsulation, thereby preventing surface defects and improving wafer warpage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuits of different sizes are packaged together in 3D stacking, then integration density and bandwidth are improved, but asymmetric wafer warpage and surface defects occur
Solution Approach 1:
A dummy substrate is introduced as an intermediary component between the first integrated circuit (larger size) and the second integrated circuit (smaller size). This dummy substrate acts as a mediator to balance the thermal expansion characteristics and mechanical properties across the stacked structure, preventing asymmetric wafer warpage while enabling the integration of circuits with different footprints. The dummy substrate's coefficient of thermal expansion is specifically matched to compensate for size differences between the integrated circuits.
2Productivity
If integrated circuits of different sizes are packaged together in 3D stacking, then integration density and bandwidth are improved, but surface defects like crystal originated pits occur
Solution Approach 1:
The dummy substrate serves as a protective intermediary that prevents direct contact and potential damage between the first and second integrated circuits of different sizes. This intermediary layer eliminates surface defects such as crystal originated pits by providing a compliant interface that accommodates size mismatches and prevents mechanical stress concentration at the interfaces of differently-sized circuits.
3Manufacturing precision
If a dummy substrate is added to compensate for size differences, then wafer warpage control and surface quality are improved, but device complexity increases
Solution Approach 1:
The dummy substrate is designed with a coefficient of thermal expansion that matches or complements the integrated circuits, creating a homogeneous thermal-mechanical environment across the stacked package. This homogeneity in thermal expansion properties allows the dummy substrate to seamlessly integrate with the existing circuit components, minimizing additional complexity while achieving effective warpage control. The dummy substrate essentially becomes a compatible extension of the existing circuit structure rather than a foreign element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures better wafer warpage control and prevents surface defects like crystal originated pits, allowing for more efficient and reliable packaging of integrated circuits with different sizes by compensating for size differences and ensuring a planar surface for subsequent processes.
Implementation Method 1
a dummy substrate 108 with a similar coefficient of thermal expansion to the integrated circuits
Data Source
AI summary
A package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer.


