Dummy Tiling for Charge Protection in Memory Arrays
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Solution Overview
Problem
In-line charging during semiconductor manufacturing causes non-uniform charge distributions, leading to poor memory performance, increased leakage current, and electrostatic discharge (ESD) issues, which are difficult to model and measure, and result in device failure and electromagnetic interference.
Innovation Solution
Implementing dummy tiles with a variable oxide thickness and a polysilicon cap to form a charge trapping region, acting as a 'charge drain' to protect devices from ESD events and create a more uniform charge distribution by connecting to the device through a poly-bridge, which can later be etched away.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used, then production cost and complexity are controlled, but charge distribution uniformity and device reliability deteriorate due to in-line charging and ESD events
Solution Approach 1:
The dummy tiles are formed during the manufacturing process before the actual device operation, pre-establishing charge dissipation pathways. The thin oxide regions are created in advance to provide low-impedance paths for charge drainage, preventing charge accumulation before ESD events can occur.
Solution Approach 2:
The dummy tiles act as intermediary structures between the plasma processing environment and the sensitive device regions. These tiles with thin oxide layers serve as mediator elements that intercept and dissipate charging effects, protecting the actual memory devices from direct exposure to harmful charge accumulation.
2Reliability
If dummy tiles with thin oxide layers are added to protect against charging, then charge distribution uniformity and device reliability improve, but manufacturing complexity and process steps increase
Solution Approach 1:
The dummy tiles perform multiple functions: they serve as charge dissipation structures during manufacturing, act as structural fillers to improve plasma uniformity across the wafer surface, and can be integrated with existing memory cell patterns. This multi-functionality justifies the additional structural elements.
Solution Approach 2:
The invention changes the oxide thickness parameter locally in dummy tile regions compared to standard device regions. By creating thin oxide regions (different parameter value) in specific locations, the structure provides low-impedance charge paths without requiring complete redesign of the entire device architecture.
3Productivity
If plasma processing is used for manufacturing, then manufacturing efficiency and productivity are maintained, but in-line charging and ESD events occur causing device failure
Solution Approach 1:
The invention converts the harmful plasma-induced charging effect into a beneficial self-regulating mechanism. The thin oxide regions in dummy tiles have lower breakdown voltages, so they preferentially undergo dielectric breakdown and dissipate charge during plasma processing. This converts the harmful charging effect into a useful charge drainage mechanism that protects sensitive device regions.
Solution Approach 2:
The dummy tiles are positioned and configured to counteract the charging effects before they can damage the actual devices. The thin oxide regions are pre-positioned to intercept charge accumulation, providing preliminary protection against in-line charging damage during plasma processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces ESD events, improves charge distribution uniformity, and enhances the operational lifetime of semiconductor devices by acting as a protective 'charge drain', thereby increasing production yields and reducing device failure.
Implementation Method 1
dummy tiles with a variable oxide thickness and a polysilicon cap form a charge trapping region
Implementation Method 2
Charge can also accumulate on a semiconductor surface until catastrophic breakdown or an electrostatic discharge (ESD) event occurs
Implementation Method 3
The damage can result when ions and electrons are introduced by a plasma process bombarding the surface of a metal structure
Implementation Method 4
Implanted dopant ions, well known in the art, are electrically charged, a consequence of the ion implantation process
Data Source
AI summary
Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.