Dummy Trench Gate Segmentation for Capacitance Control
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Solution Overview
Problem
Conventional semiconductor devices with trench gates and dummy trench gates exhibit peculiar capacitance-voltage characteristics, leading to gate voltage oscillation and switching malfunctions, especially in structures with a ⅚ thinning placement ratio of 1:5.
Innovation Solution
The semiconductor device incorporates a configuration where first and second dummy trench gates are disposed between trench gates, electrically connected to a main electrode, and arranged to bring the pn junction close to a parallel plate capacitor configuration, preventing peculiar capacitance-voltage characteristics by ensuring uniform depletion layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy trench gates are provided deeper than trench gates in a 1:5 placement ratio, then the semiconductor device structure is simplified and manufacturing is easier, but peculiar capacitance-voltage characteristics occur causing gate voltage oscillation and switching malfunction
Solution Approach 1:
The dummy trench gates are segmented into two distinct depth levels: first dummy trench gates extending to a first depth and second dummy trench gates extending to a second depth greater than the first depth. This segmentation creates a stepped configuration that prevents peculiar capacitance-voltage characteristics while maintaining manufacturing simplicity through selective etching and filling processes.
Solution Approach 2:
Different regions of the dummy trench gates are assigned different depths locally. The first dummy trench gates have a first depth while the second dummy trench gates have a greater second depth. This local variation in depth creates uniform depletion layers across different regions, eliminating the capacitance-voltage peculiarities that would occur with uniform depth structures.
2Reliability
If dummy trench gates are made deeper than trench gates, then field control is improved, but non-uniform depletion layers form causing peculiar capacitance-voltage characteristics
Solution Approach 1:
The dummy trench gates are divided into two depth groups: first dummy trench gates at a first depth and second dummy trench gates at a greater second depth. This segmentation strategy creates a stepped profile that ensures uniform depletion layer formation across all dummy trench gate regions, preventing the non-uniform depletion layers that would result from a single uniform depth configuration.
Solution Approach 2:
The depth parameter of the dummy trench gates is changed across different regions rather than maintaining a uniform value. By varying the depth parameter locally (first depth for some dummy trench gates, second greater depth for others), the invention achieves uniform depletion layer characteristics and eliminates peculiar capacitance-voltage behavior while maintaining effective field control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents the occurrence of peculiar capacitance-voltage characteristics, enhancing the switching operation speed and reducing switching losses by allowing the capacitance to be calculated as a parallel plate capacitor, thus improving the device's performance.
Implementation Method 1
peculiar capacitance-voltage characteristics
Data Source
AI summary
Provided is a semiconductor device including: a semiconductor substrate having at least first and second semiconductor layers of a first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the first conductivity type selectively provided in an upper layer portion of the third semiconductor layer; a trench gate passing through the fourth and third semiconductor layers in a thickness direction to penetrate into the second semiconductor layer; a first dummy trench gate passing through the third and second semiconductor layer in the thickness direction to penetrate into the first semiconductor layer; and a second dummy trench gate passing through the third semiconductor layer in the thickness direction to penetrate into the second semiconductor layer, the first and second dummy trench gates being disposed between the trench gates arrayed and being electrically connected to a first main electrode.