Dummy TSV Heat Dissipation in 3D Stacked Chips
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Solution Overview
Problem
The challenge in 3D semiconductor packaging is to enhance heat removal and process uniformity in densely packed stacked die devices, where conventional solutions struggle with heat dissipation and fabrication processing due to the limitations of traditional through-silicon-via (TSV) structures.
Innovation Solution
The method involves forming shallow 'dummy' TSV structures above or below active circuit areas, with controlled etching to create TSVs of different depths, allowing dummy TSVs to be positioned close to active circuits for improved heat dissipation and process uniformity without additional processing steps, by making the feature size of dummy TSVs smaller than real TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional TSV structures are used in stacked die devices, then through-silicon-via connectivity is achieved, but heat dissipation and process uniformity deteriorate due to non-uniform TSV distribution and limited heat removal paths
Solution Approach 1:
The patent segments TSV structures into two types: real TSVs that extend through the entire silicon thickness for electrical connectivity, and dummy TSVs that extend only partially through the silicon to provide heat dissipation paths. This segmentation allows different TSV functions to be optimized independently, improving overall heat removal while maintaining process uniformity through consistent etching parameters
Solution Approach 2:
The patent applies local quality by positioning dummy TSVs specifically over active circuit areas where heat generation is highest, while real TSVs are positioned for electrical connectivity. This localized approach concentrates heat dissipation capacity where it is most needed, improving thermal management without requiring uniform TSV distribution throughout the entire device
2Temperature
If dummy TSVs are positioned close to active circuits for improved heat dissipation, then thermal performance improves, but the risk of damaging active circuits increases
Solution Approach 1:
The patent applies partial action by forming dummy TSVs that extend only partially through the silicon substrate, stopping before reaching the active circuit region. This partial penetration provides sufficient heat dissipation proximity to active circuits while maintaining a safety margin that prevents direct contact and potential damage to sensitive circuit elements
Solution Approach 2:
The patent utilizes parameter changes in the etching process, specifically varying the etch depth parameter to create two distinct TSV types from the same etching conditions. By controlling the etch depth to stop at a predetermined distance from active circuits, the process achieves optimal heat dissipation while ensuring circuit protection through parameter-based precision control
3Temperature
If different depth TSVs are formed using etching processes, then heat dissipation improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by using a single etching process to accomplish multiple functions: forming both real TSVs for electrical connectivity and dummy TSVs for heat dissipation. The process achieves differentiation through pattern design and etch depth control rather than requiring separate etching steps, maintaining manufacturing simplicity while enabling diverse TSV functionality
Solution Approach 2:
The patent exploits parameter changes in the etching process, particularly the relationship between feature size and etch rate, to naturally produce different TSV depths from the same etching conditions. Larger feature sizes result in deeper etching, allowing real and dummy TSVs to be formed simultaneously with appropriate depth differentiation without additional process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat dissipation and process uniformity by allowing dummy TSVs to be located wherever needed, improving thermal resistance and manufacturing stability, applicable to stacked die architectures like graphics and CPU chips.
Implementation Method 1
The etching process is controlled to form the 'dummy' and 'real' TSVs at different depths by making the feature size of the 'dummy' TSV structures smaller than the feature size of the 'real' TSV structures. The differing depths of TSV structures results from the fact that the etching ratio of a structure is different depending on a feature size.
Implementation Method 2
The positioning of the dummy TSV structures in close proximity to the specified active circuit improves heat dissipation as compared to using only TSV structured outside of the active areas.
Data Source
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AI summary
In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.