Dummy UBM Structure for Isolated High-Density RDL Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in improving integration density and reducing device defects while maintaining device performance, particularly in the formation of dummy bumps over redistribution layers (RDLs) and conductive traces, where existing methods fail to ensure adequate shear strength and electrical isolation.
Innovation Solution
The method involves forming a passivation structure with multiple layers, including oxide and nitride layers, and creating openings for active and dummy bumps, where the dummy bumps extend through the polymer and passivation structures, ensuring electrical isolation from RDLs and conductive traces, and include via portions for enhanced adhesion and shear strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dummy bumps are formed over RDLs and conductive traces without adequate isolation, then device integration density improves, but electrical isolation and device reliability deteriorate
Solution Approach 1:
The patent divides the isolation structure into multiple segments: a first insulating layer directly over the conductive trace, a second insulating layer over the first insulating layer, and a via structure penetrating through these layers. This segmented approach provides adequate electrical isolation while allowing dummy bumps to be formed over the conductive traces, thus resolving the contradiction between integration density and electrical isolation.
2Ease of manufacture
If dummy bumps are formed without via portions, then manufacturing complexity reduces, but shear strength and bonding reliability deteriorate
Solution Approach 1:
The dummy bump structure is formed as a composite comprising a bump material and a via structure. The via structure penetrates through the insulating layers and makes contact with the underlying conductive trace, creating a composite structure that provides both mechanical support for shear strength and electrical connectivity, while remaining integrated into a single manufacturing process.
3Area of stationary object
If routing area is limited, then device area reduces, but routing capability and device performance deteriorate
Solution Approach 1:
The patent utilizes the vertical dimension by forming via structures that penetrate through multiple insulating layers. This allows conductive traces to be routed in the horizontal plane while dummy bumps and via structures occupy the vertical space, effectively adding a third dimension to the design and increasing routing capability without proportionally increasing the device footprint.
Data Source
AI summary
Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.