Dummy-Via Interconnect Structure for CMP-Friendly Fine Metal Pitch
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices with high device density and performance requires improved resistance and capacitance (RC) characteristics, but existing technologies face challenges in achieving these while avoiding issues like short-circuiting and bridging due to fine metal pitches and misalignment during manufacturing processes.
Innovation Solution
The proposed solution involves an interconnect structure that includes active top vias and dummy top vias, formed through a combination of top via and damascene processes. The active top vias are connected to overlying metal lines, while dummy top vias are not connected, facilitating easier detection during chemical-mechanical polishing (CMP) operations to prevent via loss and CMP dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine metal pitches are used to achieve high device density, then device density is improved, but the risk of short-circuiting and bridging increases
Solution Approach 1:
The patent applies preliminary action by forming dummy top vias in advance before the actual top via formation. These dummy vias serve as markers that guide subsequent processing steps, ensuring proper alignment and preventing misalignment-induced short circuits. The dummy vias are removed after serving their guiding function, having prevented the harmful short-circuiting effect.
Solution Approach 2:
The patent uses dummy top vias as intermediary elements during the manufacturing process. These dummy vias act as temporary mediators that facilitate precise alignment and detection during CMP operations. They are not part of the final functional interconnect but enable the reliable formation of fine-pitch metal structures by mediating the alignment process.
2Ease of manufacture
If top via process is used to form vias, then via formation is simplified, but via loss and CMP dishing occur
Solution Approach 1:
The patent introduces dummy top vias as intermediary reference structures during the CMP process. These dummy vias provide consistent mechanical reference points that enable uniform CMP polishing, preventing dishing. They are removed after serving their function as CMP process control markers, having prevented the manufacturing precision degradation.
Solution Approach 2:
The dummy top vias provide visual and mechanical feedback during the CMP process, allowing operators to monitor polishing uniformity and detect potential via loss conditions. This feedback mechanism enables real-time process adjustment, preventing the CMP dishing and via loss that would otherwise occur in the simplified top via process.
3Manufacturing precision
If dummy top vias are added to facilitate CMP detection, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the via formation process into distinct functional components: functional top vias for electrical connection and dummy top vias for process control. This segmentation allows the dummy vias to be independently managed and removed after serving their detection function, preventing permanent addition of structural complexity to the final device.
Solution Approach 2:
The dummy top vias are temporary structures that are discarded after serving their purpose in CMP detection and alignment. Their removal recovers the device from the more complex intermediate state back to the final functional state, ensuring that the temporary complexity increase does not persist in the finished product.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the connection performance of semiconductor devices by reducing the risk of short-circuiting and bridging, while also improving the planarity and uniformity of the interconnect structure, thus maintaining the required RC characteristics.
Implementation Method 1
chemical-mechanical polishing (CMP) operations
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3B
AI summary
Provided is a semiconductor device which includes: a transistor structure; a plurality of 1st metal lines (M11, M12, M13, M14, M15) above the transistor structure; and a plurality of 1st vias (dV, ATV) formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines (M11, M12, M13, M14, M15); a 2nd via (DV) formed on a 1st via (ATV) among the plurality of 1st vias (dV, ATV); and a 2nd metal line (M22) on the 2nd via (DV), wherein the 1st metal lines (M11, M12, M13, M14, M15) are arranged in a 1st direction (D1) and extended in a 2nd direction (D2) which intersects the 1st direction (D1), and the 2nd metal line (M22) is extended in the 1st direction (D1), and wherein the plurality of 1st vias (dV, ATV) comprise at least one dummy via (dV) which is not connected to any metal line thereabove other than an underlying 1st metal line among the selected 1st metal lines.