Dummy Via Structure for Multi-Stacked Chip Delamination Control
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Solution Overview
Problem
Devices with multi-stacked chips suffer from delamination between chips due to stresses at the center, particularly in the device region where the substrate layer deforms or the dielectric film between chips delaminates.
Innovation Solution
Incorporation of dummy vias within the device region of the device chip provides structural support, preventing inter-chip or inter-layer delamination by offsetting active TSVs and maintaining space for active devices without introducing additional through vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate vias (TSVs) are used to connect multi-stacked chips, then electrical connectivity between chips is achieved, but mechanical stresses cause delamination and deformation at the center of the device region
Solution Approach 1:
The patent divides the via structure into two segments: active TSVs for electrical connectivity and dummy vias for structural support. The dummy vias are non-conductive and do not extend through the entire substrate thickness, creating a segmented approach where different via types serve different functions. This segmentation allows the structure to maintain electrical connectivity while preventing stress-induced delamination in the device region.
Solution Approach 2:
The dummy vias act as intermediary structural elements that mediate between the active TSVs and the substrate. These dummy vias provide mechanical support and distribute stresses without creating conductive paths, effectively serving as a mediator that protects the device region from stress concentration while allowing active TSVs to maintain electrical connectivity.
2Stability of the object's composition
If additional through vias are added to the device region to provide structural support, then delamination risk is reduced, but space for active devices is reduced and device complexity increases
Solution Approach 1:
The patent applies local quality by making vias in different regions have different properties. In the peripheral region, full-length active TSVs provide both connectivity and support. In the device region, shorter dummy vias provide only structural support without electrical connectivity. This local differentiation optimizes the structure by providing support where needed without adding unnecessary complexity or consuming device space.
Solution Approach 2:
The dummy vias perform a partial function - they provide structural support but intentionally do not provide electrical connectivity. By making the vias non-conductive and limiting their depth (not extending through the entire substrate), the patent achieves sufficient structural support without the excessive action of creating full through-vias that would increase complexity and reduce device space.
3Area of stationary object
If active TSVs are positioned in the peripheral region only, then device region space is maximized, but structural support at the center is insufficient causing deformation
Solution Approach 1:
The patent segments the via distribution into peripheral active TSVs and central dummy vias. This segmentation allows the peripheral region to maintain maximum device area while the central dummy vias provide the necessary structural rigidity. The dummy vias are strategically positioned in the device region to provide local reinforcement without encroaching on active device space.
Solution Approach 2:
The dummy vias are essentially copies of the TSV structure (similar geometry and material composition) but modified to be non-conductive and shorter. This copying approach allows the structural support function to be achieved using a familiar via-like structure, maintaining manufacturing simplicity while providing the needed structural reinforcement in the device region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy vias effectively reduce or eliminate the risk of delamination and deformation in multi-stacked chip devices by enhancing structural rigidity and absorbing mechanical stresses, including thermal expansion.
Implementation Method 1
absorbing mechanical stresses, including thermal expansion
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor device including a device substrate having a front-side surface opposite a back-side surface. An upper dielectric layer is disposed over the back-side surface. A through substrate via (TSV) extends from the upper dielectric layer through the device substrate. A dummy via is laterally offset from the TSV. A top surface of the dummy via and a top surface of the TSV are co-planar, and a bottom surface of the dummy via is separated from the front-side surface by the device substrate.