Dummy Via Etching for Precise M2 Trench Shape Control

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Solution Overview

Problem

Conventional semiconductor manufacturing processes for M2 trench etching face challenges in achieving accurate dimensions and shape, leading to potential electrical performance deterioration due to fencing issues during the etching process.

Innovation Solution

A method involving a two-step etching process using different etching gases (CHF3 and O2 for the first etching process, and H2 and N2 for the second etching process) to form a dummy via with a depth of equal to or less than 200 nm, ensuring the top surface is lower than the low-k material layer and higher than the bottom surface, thereby addressing the fencing problem and improving electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional etching processes are used for M2 trench, then the manufacturing process is simple, but the accuracy of the scale and shape of the structure deteriorates leading to fencing problems

Engineering Contradiction:
Improveaccuracy of scale and shape of M2 trenchVSAvoidcomplexity of etching process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The etching process is divided into multiple sequential steps with different etching gases and parameters. The first etching step uses one gas composition to create initial structure, followed by a second etching step with different gas composition to refine the trench shape and dimensions, thereby achieving high manufacturing precision through process segmentation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes etching parameters including gas composition, pressure, power, and temperature between different etching steps. By adjusting these parameters sequentially, the process achieves precise control over the M2 trench scale and shape, resolving the contradiction between simplicity and precision

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the dummy via is etched deeper to improve electrical performance, then resistivity decreases, but the risk of fencing problems increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidfencing problem
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent carefully controls etching parameters including depth, gas composition, and power settings to achieve the optimal balance. By adjusting these parameters, the dummy via is etched to a depth that improves electrical performance while maintaining structural integrity and avoiding fencing problems

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The multi-step etching process allows for intermediate inspection and adjustment. After the first etching step, the process state can be evaluated and parameters for the second step are adjusted accordingly, ensuring the final structure achieves desired electrical performance without fencing issues

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the quality of dummy vias, reduces resistivity, and improves the electrical performance of semiconductor devices by precisely controlling the etching process and avoiding fencing issues.

Implementation Method 1

performing a first etching process and a second etching process different from the first etching process, in which performing the first etching process etches a first portion of the dummy via with a first depth, and performing the second etching process etches a second portion of the dummy via with a second depth

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS20240413006A1Method of manufacturing semiconductor device
Publication Date: 2024.12.12 NAN YA TECH
  • US20240413006A1 patent drawing
  • US20240413006A1 patent drawing
  • US20240413006A1 patent drawing

AI summary

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a dummy via in a trench of a stacking structure with a bottom anti-reflection coated material, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and removing a portion of the dummy via by performing a first etching process and a second etching process, and in which the first etching process and the second etching process are performed such that a top surface of the dummy via is lower than a top surface of the low-k material layer and higher than a bottom surface of the low-k material layer.