Dummy Through-Via Layout for RDL Crack Resistance
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Solution Overview
Problem
The challenge in semiconductor packaging is the risk of cracking in redistribution lines due to thermal expansion, particularly in regions with mismatched coefficients of thermal expansion, such as the edges and corners of encapsulated integrated circuit dies, which affects the reliability of the devices.
Innovation Solution
Formation of dummy through vias in regions with mismatched thermal expansion coefficients to suppress the thermal expansion of the encapsulant, thereby reducing the risk of cracking in redistribution lines, especially for small-sized and closely pitched lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If redistribution lines are made small-sized and closely pitched to increase integration density, then component density is improved, but the risk of cracking due to thermal expansion increases
Solution Approach 1:
The patent applies local quality by placing dummy through vias specifically at border regions where thermal expansion mismatch is most severe, rather than uniformly distributing them. This targeted approach addresses the local thermal stress problem at edges and corners without adding unnecessary structures in regions where redistribution lines are already protected, thus maintaining component density while preventing cracking in critical areas.
Solution Approach 2:
The dummy through vias are formed before the final packaging process, preliminarily establishing thermal expansion compensation structures in place. This preliminary action allows the redistribution lines to be designed with small sizes and close pitches without worrying about subsequent thermal cracking, as the protective dummy vias are already positioned to mitigate thermal stress during operation.
2Reliability
If dummy through vias are formed to suppress thermal expansion, then reliability is improved, but device complexity increases
Solution Approach 1:
The dummy through vias are strategically placed only at border regions where thermal expansion mismatch occurs, rather than adding complex structures throughout the entire device. This localized approach improves reliability where needed without unnecessarily increasing overall device complexity in regions where thermal stress is not a problem.
Solution Approach 2:
The dummy through vias are simple replicated structures that copy the basic via geometry without requiring complex multi-layer or multi-material constructions. This copying approach provides effective thermal expansion suppression through repeated simple structures, avoiding the need for complex via designs while still achieving the reliability improvement.
3Reliability
If dummy through vias are formed in border regions, then thermal stress is mitigated, but manufacturing precision requirements increase
Solution Approach 1:
The dummy through vias are concentrated in specific border regions where thermal expansion mismatch is physically determined by material properties and geometry, not by complex design decisions. This local quality approach defines precise placement locations based on thermal physics principles, making the precision requirements inherent to the problem rather than imposed by arbitrary design choices.
Solution Approach 2:
The formation of dummy through vias is integrated into the preliminary packaging process steps, establishing precise placement locations before final assembly. This preliminary action allows manufacturing systems to pre-position the dummy vias with controlled precision during the packaging workflow, rather than requiring ultra-precise placement after all other components are assembled.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dummy through vias enhance the reliability of semiconductor devices by mitigating thermal stress, ensuring the integrity of redistribution lines and improving the overall performance of the integrated circuit packages.
Implementation Method 1
mismatch in coefficients of thermal expansion, such as proximate the border (e.g., edges and/or corners) of an encapsulated integrated circuit die. Forming the dummy through vias in such regions may help suppress thermal expansion of the encapsulant during operation or testing.
Data Source
AI summary
In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.