Dummy Wiring Chip Strength Reinforcement for Semiconductor Reliability

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Solution Overview

Problem

Semiconductor devices with low dielectric constant interlayer insulating films face issues such as peeling or cracking due to thermal and mechanical stress, which conventional chip strength reinforcement techniques inadequately address, leading to potential leakage or disconnection between wiring layers.

Innovation Solution

The implementation of a semiconductor device with a chip strength reinforcement system using dummy wiring structures that extend across multiple wiring layers, including the bottommost and topmost layers, to distribute stress and enhance mechanical strength, particularly in the thickness direction, thereby preventing peeling or cracking of the interlayer insulating film.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If low dielectric constant material is used for interlayer insulating film, then parasitic capacitance is reduced and device speed is enhanced, but the film becomes susceptible to peeling and cracking due to low mechanical strength and poor adhesion

Engineering Contradiction:
Improvedevice speedVSAvoidmechanical strength of interlayer insulating film
Core Design Contradiction:
SpeedVSStrength

Solution Approach 1:

The patent uses a composite structure combining low-k dielectric material with organic resin material. The low-k material (first interlayer insulating film) provides low parasitic capacitance for high-speed operation, while the organic resin material (second interlayer insulating film) provides mechanical strength and adhesion. This composite approach allows simultaneous achievement of electrical performance and mechanical reliability.

Inventive Principle:
Principle #40Composite materials

2Strength

If dummy wiring structure is provided as chip strength reinforcement, then mechanical strength is improved, but stress concentrates on the dummy wiring structure causing peeling of interlayer insulating film

Engineering Contradiction:
Improvechip strengthVSAvoidadhesion of interlayer insulating film
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent applies different materials with different properties to different regions/layers. The first interlayer insulating film uses low-k material for electrical performance, while the second interlayer insulating film uses organic resin material for mechanical reinforcement. This local differentiation of material properties allows each layer to fulfill its specific function without causing stress concentration and peeling.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8237281B2Semiconductor device
Publication Date: 2012.08.07 NUVOTON TECH CORP JAPAN
  • US8237281B2 patent drawing
  • US8237281B2 patent drawing
  • US8237281B2 patent drawing

AI summary

A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.