Dummy Word Line Capacitive Coupling for SRAM Read/Write Assist
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Solution Overview
Problem
Integrated circuits, particularly memory chips like SRAM, face challenges in read and write operations due to process variations, leading to difficulties at certain corners (e.g., slow-fast and fast-slow corners), which existing read/write assist techniques often address at the cost of increased chip area and power consumption.
Innovation Solution
The integration of a dummy word line (DWL) capacitively coupled with the word line (WL) to assist in voltage control during read and write operations, using capacitive coupling to boost or reduce the WL voltage, thereby enhancing the performance without significant area or power penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy word line is added to provide read/write assist, then memory operation reliability is improved, but chip area increases
Solution Approach 1:
The patent introduces a dummy word line arranged in a different spatial dimension (parallel to the original word line) to provide capacitive coupling assistance. This dimensional addition enables read/write assist functionality without interfering with the original memory cell structure, resolving the contradiction between reliability improvement and area consumption.
2Productivity
If existing read/write assist techniques are implemented, then memory performance is improved, but power consumption increases
Solution Approach 1:
The dummy word line acts as an intermediary element that provides capacitive coupling to assist memory operations. By using this intermediate structure, the patent achieves improved memory performance through voltage boosting during read/write operations while consuming less power compared to traditional assist techniques that directly modify memory cell transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the read and write assist capabilities of SRAMs by reducing the access time and increasing the noise margin, while maintaining efficiency and minimizing the impact on chip area and power consumption.
Implementation Method 1
a dummy word line arranged with the word line to have a capacitance therebetween
Implementation Method 2
dummy word line means for affecting a voltage applied to the word line through a capacitive coupling therebetween
Data Source
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AI summary
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.