Dummy Wordline Contacts for Uniform Etching in 3D Staircase NAND
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Solution Overview
Problem
Semi-isolated wordline contacts in 3D NAND structures face issues of under-etch and over-etch due to non-uniform polymer deposition during etching, leading to process margin challenges and reduced device yield, especially with increased densities and smaller critical dimensions.
Innovation Solution
Incorporating dummy connectors near semi-isolated wordline contacts to alter etch characteristics, making them more uniform and reducing the risk of under-etch or over-etch by acting as floating contacts that do not fully connect to the wordlines, thus mimicking the etch characteristics of normal contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etch process tuning is used to reduce polymer deposition during etch, then poly selectivity is improved, but process margin between under-etch and over-etch is significantly reduced
Solution Approach 1:
The patent applies different etch conditions to different regions: semi-isolated contacts receive enhanced polymer deposition (through adjusted etch parameters) while normal contacts maintain standard conditions. This local differentiation allows each region to achieve optimal etch characteristics without compromising overall process margin
Solution Approach 2:
The patent changes etch parameters (gas flow rates, power, pressure) specifically for semi-isolated contact regions to increase polymer deposition during etch. This parameter adjustment compensates for the tapered profile and prevents under-etch while maintaining poly selectivity through selective application
2Reliability
If critical dimension sizing is tuned to provide adequate etch characteristics for both semi-isolated and dense wordline contacts, then device yield is improved, but process sensitivity increases with scale up
Solution Approach 1:
The patent implements region-specific etch parameter adjustments where semi-isolated contacts receive enhanced polymer deposition conditions while densely packed contacts use standard parameters. This eliminates the need to compromise center process CD sizing and reduces process sensitivity to scaling
Solution Approach 2:
The patent introduces an intermediary process step that selectively modifies etch conditions for semi-isolated contacts based on their geometric characteristics. This intermediary approach allows independent optimization of each contact type without increasing overall process sensitivity
3Quantity of substance
If increased 3D NAND densities are achieved with smaller process geometries and feature spacing, then storage capacity is improved, but etch margin of semi-isolated wordline contacts deteriorates
Solution Approach 1:
The patent adjusts etch parameters (increasing polymer deposition) specifically for semi-isolated contacts in high-density regions. This compensates for the reduced etch margin caused by smaller geometries and tapered profiles, maintaining manufacturing precision despite increased storage density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the etch margin and process stability, significantly reducing failure rates and maintaining device yield by ensuring consistent contact formation across varying densities and aspect ratios.
Implementation Method 1
nonuniform polymer deposition of a semi-isolated wordline contact can be due to a micro loading effect of high aspect ratio etches
Data Source
AI summary
A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.