Dummy Wordline Underdrive Circuitry for Memory Offset Compensation
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Solution Overview
Problem
Existing memory devices face challenges in efficiently recovering degraded read and write margins due to bitcell current offset, leading to performance penalties at the power, performance, and area (PPA) corner, as current compensation methods result in delays that are not optimal for both read and write operations.
Innovation Solution
The implementation of dummy wordline (DWL) underdrive circuitry, which underdrives the dummy wordline by an amount equal to the bitcell offset, using transistors like PMOS and NMOS bleeder transistors to generate a wordline underdrive proportional to the source voltage, thereby minimizing performance penalties and tracking read current offsets effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional delays are added to the data signal path to compensate for bitcell current offset, then read and write margins are recovered, but performance is degraded at the PPA corner
Solution Approach 1:
The patent segments the compensation mechanism into two independent paths: a dummy bitline path for measuring offset and a real bitline path for data operation. The dummy bitline discharge cells measure the offset without affecting the critical data path timing, allowing compensation without performance penalty at the PPA corner.
Solution Approach 2:
The patent introduces a dummy bitline as an intermediary that replicates the bitcell offset effects without being part of the critical data path. This intermediary allows offset measurement and compensation calculation without adding delays to the actual data signal path, thus maintaining performance while recovering margins.
2Speed
If the number of discharge cells is reduced to improve performance, then speed increases, but read and write margins are degraded
Solution Approach 1:
The patent separates the margin measurement function (performed by dummy bitline discharge cells) from the data operation function (performed by real bitline discharge cells). This allows the real bitline to use fewer discharge cells for higher speed while the dummy bitline independently measures offset to enable compensation, thus achieving both speed and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the dummy bitline measures the offset and this information is used to adjust the compensation applied to the real bitline. This feedback loop allows the system to maintain adequate margins even with reduced discharge cells in the critical path, enabling higher operating speeds.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to a dummy wordline load via a dummy wordline. The integrated circuit may include underdrive circuitry coupled to the dummy wordline between the dummy wordline driver and the dummy wordline load. The underdrive circuitry may generate an underdrive on the dummy wordline when the dummy wordline is selected and driven by the dummy wordline driver.