Duo-level word line driver circuit for memory cells
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Solution Overview
Problem
Existing word line drivers in memory circuits require additional transistors to manage higher word line voltages, leading to increased area and cost, as well as potential transistor damage over time.
Innovation Solution
A word line driver design that includes a pair of cross-coupled transistors without mirrored circuits, occupying less area and consuming less power, while providing at least two levels of word line voltage using a cascaded portion formed by at most two transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional transistors are added to manage higher word line voltages, then voltage management capability is improved, but area and cost increase
Solution Approach 1:
The word line driver circuit is designed to provide multiple voltage levels (first voltage level for reading, second voltage level for writing) using the same transistor components. The circuit achieves multi-functionality by selectively coupling different power supply levels to the memory cell through the cross-coupled transistor configuration, eliminating the need for separate voltage management circuits for different operations.
Solution Approach 2:
The patent merges the voltage management functionality into the existing word line driver circuit by using shared transistors and power supply connections. Instead of adding separate voltage management transistors, the design combines read and write voltage delivery paths within the same circuit topology, reducing overall component count and area.
2Adaptability or versatility
If additional transistors are added to manage higher word line voltages, then voltage management capability is improved, but power consumption increases
Solution Approach 1:
The same transistor components perform multiple functions including voltage switching, data writing, and data reading operations. By making the transistors universal rather than specialized, the circuit avoids the continuous operation of dedicated voltage management transistors, thereby reducing overall power consumption while maintaining adaptability.
3Productivity
If higher word line voltages are applied to memory cells, then writing efficiency is improved, but transistor reliability deteriorates
Solution Approach 1:
The circuit dynamically adjusts the voltage level applied to memory cells based on the operation type. During write operations, the second power supply provides higher voltage to improve writing efficiency. During read operations, the first power supply provides lower voltage to protect transistors from damage. This dynamic voltage adjustment resolves the contradiction between writing efficiency and transistor reliability.
4Area of stationary object
If cross-coupled transistors without mirrored circuits are used, then area is reduced, but circuit complexity increases
Solution Approach 1:
The patent extracts and removes the mirrored circuit portion from the traditional word line driver design, retaining only the essential cross-coupled transistor configuration. This extraction reduces area by eliminating redundant components while the cross-coupled structure itself provides sufficient functionality for voltage management and data operations.
Data Source
AI summary
A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.