Duobinary Receiver Clocked Comparator Switching for Lower Power
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Solution Overview
Problem
Conventional duobinary receivers require multiple comparators to operate, increasing load and power consumption due to the need for equalization, which affects the efficiency of signal processing.
Innovation Solution
A duobinary receiver design that includes a signal dividing circuit using multi-phase sampling clocks, a level detecting circuit with comparing circuits synchronized by control clock signals, and a data converting circuit to decode state signals into bits, reducing the number of comparators needed by dynamically coupling them with the analog receiving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparators are coupled to the output terminal of the analog receiving circuit for equalization operation, then the decoding accuracy of duobinary signal is improved, but the load on output terminal and power consumption increase
Solution Approach 1:
The patent applies dynamics by making the coupling between comparators and the analog receiving circuit dynamic rather than static. The comparators are selectively coupled only when needed for equalization operations, and decoupled during normal operation. This dynamic configuration allows the system to achieve high decoding accuracy when equalization is required while minimizing power consumption and load during normal operation, thus resolving the contradiction between decoding accuracy and power consumption.
2Adaptability or versatility
If multiple comparators are coupled to the output terminal of the analog receiving circuit, then the equalization operation capability is improved, but the device complexity increases
Solution Approach 1:
The patent uses dynamic switching to control the coupling between comparators and the analog receiving circuit. A control signal selectively enables or disables the connection based on whether equalization is needed. This approach provides full equalization capability when required while keeping the device structure simple during normal operation, as the comparators remain inactive and disconnected from the signal path.
Solution Approach 2:
The patent implements periodic action by alternating between two operational modes: normal reception mode where comparators are decoupled, and equalization mode where comparators are coupled. This periodic switching between operational states allows the system to possess equalization capability without permanently incorporating the complexity of multiple comparators into the active signal path.
3Reliability
If a total of four comparators are always coupled to the output terminal, then the duobinary signal reception is reliable, but the power consumption increases during operation
Solution Approach 1:
The patent resolves the contradiction between reliability and power consumption by dynamically controlling the coupling of comparators. During normal operation, comparators are decoupled to minimize power consumption. When signal quality degrades or equalization is needed, the comparators are coupled to ensure reliable reception. This dynamic approach maintains signal reception reliability while significantly reducing average power consumption compared to having all comparators always connected.
Data Source
AI summary
A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.