Duplex Memory I/O Circuit for Low-Latency Data Moves
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Solution Overview
Problem
Existing storage devices face inefficiencies in data move operations, leading to increased latency and wear on memory devices, which affect their lifespan and performance.
Innovation Solution
A duplex input/output circuit and memory die configuration that allows simultaneous data output from a source memory die and input into a target memory die through a duplex interface circuit, minimizing latency and overlapping processes to enhance data move operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data move operation is performed in traditional sequential manner, then device complexity is reduced, but latency increases and performance deteriorates
Solution Approach 1:
The data move operation is segmented into independent input and output processes that can execute simultaneously. The input circuit and output circuit are separated as independent functional blocks, allowing data to be received and transmitted in parallel without sequential dependency, thereby reducing latency and improving operation speed.
Solution Approach 2:
The input circuit and output circuit are merged into a single duplex I/O circuit block that handles both functions simultaneously. This integration allows the memory device to perform data reception and transmission in parallel through shared control logic and timing mechanisms, improving productivity while maintaining controlled complexity.
2Productivity
If duplex input/output circuit is implemented, then data move operation efficiency is improved, but device complexity increases
Solution Approach 1:
The duplex I/O circuit is designed as a universal interface that can simultaneously perform input, output, and data move operations. By making the circuit multi-functional rather than dedicated to single tasks, the patent improves data move efficiency without proportionally increasing complexity, as the same physical circuit serves multiple purposes through controlled operation modes.
Solution Approach 2:
A control circuit acts as an intermediary that manages the simultaneous operation of input and output circuits. This mediator coordinates timing signals and data flow directions, preventing conflicts while enabling parallel operations, thus improving efficiency without requiring complex direct interconnections between all circuit components.
3Productivity
If data move operation time is reduced, then performance is improved, but wear on memory device increases
Solution Approach 1:
Data is preliminarily received and buffered in the input circuit before being transmitted through the output circuit. This preliminary action allows data to be staged and prepared in advance, enabling faster data move operations without requiring intensive read-write cycles on the memory cells themselves, thereby reducing wear and improving reliability.
Solution Approach 2:
The input and output circuits serve as intermediary buffers between external devices and memory cells. By handling data transmission at the circuit level rather than directly accessing memory cells for every operation, the patent reduces the number of intensive write cycles on memory cells, minimizing wear and extending device lifespan while maintaining high data move speed.
Data Source
AI summary
A duplex input/output circuit of a memory die includes an output circuit and an input circuit. The output circuit receives output data from a data line coupled to a buffer region and outputs the output data to an output bus, in response to a selecting signal, a read enable signal, and an output signal. The input circuit receives input data from an input bus and output the input data to the data line, in response to the selecting signal, the read enable signal, a write enable signal, and an input signal.