Duplexed CPU Control via Synchronous Snooping for Plant Availability

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Solution Overview

Problem

Conventional duplexed CPU systems for plant control face challenges in maintaining system availability and response speed during CPU switch-over and program updates, especially over long distances, due to noise susceptibility and asynchronous data processing.

Innovation Solution

A duplexed CPU control system with synchronized communication paths allows a secondary CPU to snoop control data synchronously while the primary CPU acquires data, enabling quick switch-over and program updates without stopping the plant system, using communication paths like RS-485 for synchronization and Ethernet for less frequent synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the secondary CPU snoops memory data from the primary CPU via parallel buses, then the secondary CPU can acquire control information, but the system becomes weak against noise and unsuitable for long distance data transmission

Engineering Contradiction:
Improvenoise resistanceVSAvoiddata transmission distance
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent replaces the traditional parallel bus snooping mechanism with a communication protocol-based data transmission system. Instead of using electrical parallel buses that are susceptible to noise, the invention uses structured communication protocols with start bits, data bits, and stop bits to transmit control information, enabling reliable long-distance communication while maintaining data integrity against noise interference.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If the data frame is stored on the primary CPU for snooping, then the secondary CPU can acquire control information, but the primary and secondary CPUs cannot process data synchronically, causing time delay

Engineering Contradiction:
Improvesynchronous processingVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having the secondary CPU independently acquire control information from the control target simultaneously with the primary CPU, rather than waiting to snoop data after the primary CPU processes it. This parallel independent acquisition eliminates waiting time and enables synchronous processing between primary and secondary CPUs, maintaining fast response speed while ensuring data consistency.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If additional functions are added to enable program updating without stopping the plant system, then system availability is enhanced, but the system complexity increases

Engineering Contradiction:
Improvesystem availabilityVSAvoidsystem function complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the communication protocol and data acquisition mechanism to serve multiple functions simultaneously. The same protocol structure and acquisition process support both normal control operations and program updating operations, allowing the secondary CPU to take over seamlessly during updates without requiring separate dedicated mechanisms, thus enhancing availability while minimizing added complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9208037B2Duplexed operation processor control system, and duplexed operation processor control method
Publication Date: 2015.12.08 HITACHI LTD
  • US9208037B2 patent drawing
  • US9208037B2 patent drawing
  • US9208037B2 patent drawing

AI summary

The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target.