DUT Array Testing for BTI and TDDB Degradation Analysis
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Solution Overview
Problem
Semiconductor device manufacturing faces challenges with bias temperature instability (BTI), random telegraph noise (RTN), and time-dependent dielectric breakdown (TDDB), which affect the reliability and performance of MOSFETs, and existing testing methods lack accuracy in determining degradation parameters.
Innovation Solution
A system and method that apply stress and measurement conditions to multiple semiconductor devices under test (DUTs) in an array, allowing for concurrent stress testing and precise measurement of degradation parameters like BTI and TDDB, while maintaining stress conditions on other DUTs to enhance measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress conditions are applied to all DUTs simultaneously for reliability testing, then the testing coverage is improved, but the measurement accuracy of degradation parameters deteriorates because devices under stress cannot be measured
Solution Approach 1:
The array of DUTs is divided into multiple groups, with each group associated with a separate test column. This segmentation allows different groups to be in different states (stress or measurement) simultaneously, resolving the contradiction between comprehensive stress testing and accurate measurement.
Solution Approach 2:
The testing process alternates between applying stress conditions and measurement conditions to different groups of DUTs in a periodic manner. This allows the system to achieve both comprehensive stress coverage and accurate measurement by cycling through different test phases.
2Measurement precision
If measurement conditions are applied to determine degradation parameters, then measurement accuracy is improved, but the stress testing coverage deteriorates because devices cannot be stressed during measurement
Solution Approach 1:
By dividing the DUT array into multiple groups across different test columns, the system can apply measurement conditions to one group while simultaneously applying stress conditions to other groups, achieving both objectives in parallel.
Solution Approach 2:
The patent combines multiple test columns into a single test array, allowing simultaneous execution of stress tests and measurement tests on different groups of DUTs. This merging enables the system to achieve comprehensive testing coverage while maintaining measurement accuracy.
3Productivity
If multiple DUTs are tested in parallel to improve productivity, then the testing speed is improved, but the complexity of the testing system deteriorates
Solution Approach 1:
Each test column is designed with universal functionality to perform both stress testing and measurement tasks. This multi-functionality reduces overall system complexity compared to having separate dedicated systems for each function, while still enabling parallel testing of multiple DUTs.
Data Source
AI summary
A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.