DUT Structures in Fill Regions for Voltage Contrast Defect Detection

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Solution Overview

Problem

Conventional fabrication processes face challenges in detecting buried electrical opens and shorts in integrated circuits, leading to delayed yield learning and increased costs due to reliance on destructive and unreliable Quick Turn Monitors, as well as limited detection capabilities of optical tools.

Innovation Solution

Incorporating device under test (DUT) structures in fill regions of product dies for voltage contrast (VC) defect detection, which allows for inline, non-destructive identification of electrical defects using VC mode, enabling earlier detection of buried defects and reducing yield learning time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional fabrication processes are used for detecting electrical defects, then detection capability is limited, but yield learning time is extended by 4-6 weeks

Engineering Contradiction:

Improvedefect detection capabilityVSAvoidyield learning time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements DUT structures in fill regions that enable preliminary detection of electrical opens and shorts before final product testing. By placing dedicated test structures throughout the fabrication process, defects can be identified early in production rather than waiting for end-of-line testing, thereby reducing yield learning time while maintaining detection precision

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces DUT (Device Under Test) structures as intermediary elements between the fabrication process and defect detection. These specialized test structures serve as mediators that enable non-destructive electrical defect detection in fill regions, allowing earlier identification of opens and shorts without affecting production timelines

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If destructive Quick Turn Monitors are used for defect detection, then detection reliability is improved, but manufacturing cost increases

Engineering Contradiction:

Improvedefect detection reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent enables the fill regions to serve themselves by incorporating DUT structures that perform self-detection of electrical defects. The test structures are integrated into the fabrications process itself, allowing the manufacturing system to detect defects through non-destructive electrical testing rather than requiring separate destructive monitoring processes

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces destructive physical monitoring methods with non-destructive electrical testing using VC mode. By substituting mechanical/destructive Quick Turn Monitor approaches with electrical field-based detection through DUT structures, the system achieves reliable defect detection while reducing manufacturing costs

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Ease of manufacture

If optical tools are used for defect detection, then manufacturing simplicity is maintained, but detection capability for buried defects is limited

Engineering Contradiction:

Improvedetection process simplicityVSAvoidburied defect detection capability

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent merges the simplicity of existing fill region utilization with enhanced electrical defect detection capabilities. By combining the unused fill regions with DUT structures that perform electrical testing, the system maintains manufacturing simplicity while achieving superior detection capability for buried electrical opens and shorts

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of DUT structures in fill regions enables effective detection of electrical opens and shorts, reducing yield learning time by 4-6 weeks, minimizing costs, and establishing correlations with end-of-line yield signals, while maintaining design rule compatibility and avoiding additional footprint on the die.

Implementation Method 1

voltage contrast (VC) defect detection

Methodology Applied

Scientific EffectVoltage contrast:

Data Source

PatentUS20240329114A1Device under test (DUT) structures in fill regions of product die for voltage contrast (VC) defect detection for improved yield learning

Publication Date: 2024.10.03 INTEL CORP

AI summary

An integrated circuit on a production die comprises a device under test (DUT) cell array formed in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die. The DUT transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors. A guard ring buffer is formed at a transition between the active transistor region and the DUT cell array.