DUT Partitioning for Logic Optimization
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Solution Overview
Problem
Existing logic optimization tools for circuit design face challenges such as supporting hierarchical netlists, dealing with large DUTs, and synchronizing timing information between partitions, which leads to sub-optimal solutions and increased runtime.
Innovation Solution
The approach involves splitting the representation of a DUT into smaller sub-partitions based on timing path considerations, excluding trivial partitions from logic optimization, and inserting anchor circuit instances to maintain protected information, thereby improving logic optimization techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic optimization is performed on large DUTs with hierarchical netlists, then design functionality can be verified, but runtime increases and optimization quality deteriorates due to difficulty in synchronizing timing information between partitions
Solution Approach 1:
The DUT representation is divided into multiple partitions based on timing slacks of timing endpoints. Each partition contains timing endpoints and their transitive fan-in including optimizable leaf instances. This segmentation allows parallel processing of partitions while maintaining timing information integrity within each partition, resolving the contradiction between optimization quality and runtime.
2Device complexity
If the DUT representation is divided into multiple partitions, then processing complexity is reduced, but timing information synchronization between partitions becomes difficult leading to sub-optimal solutions
Solution Approach 1:
The DUT is segmented into partitions based on timing slacks, where each partition is self-contained with timing endpoints and their transitive fan-in. This segmentation reduces processing complexity by enabling parallel processing while maintaining timing information integrity within each partition, avoiding the need for complex inter-partition synchronization.
Solution Approach 2:
Each partition is treated as an independent unit with its own timing characteristics. The logic optimization is performed locally within each partition based on its specific timing slacks and optimizable leaf instances, rather than attempting global optimization across all partitions. This local quality approach ensures timing information accuracy within each partition while simplifying overall processing.
Data Source
AI summary
An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.