DUT Signal Evaluation via Integrated Difference

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Solution Overview

Problem

Automated Test Equipment (ATE) face challenges in accurately evaluating output signals of Devices Under Test (DUT) due to distortions like glitches and crosstalk, especially when the DUT driver is not designed to handle long cables, leading to incorrect bit level evaluations.

Innovation Solution

Generating a difference signal between the output signal of the DUT and a reference signal, integrating this difference signal over a clock period, and evaluating the integrated signal to determine the bit level, which helps tolerate distortions and reduces the impact of their occurrence time within the clock period.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a clocked comparator is used to compare the voltage level of the output signal at a predetermined point in time, then the evaluation speed is high, but the measurement precision deteriorates due to distortions like glitches and crosstalk occurring near the sampling point

Engineering Contradiction:
Improveevaluation speedVSAvoidbit level evaluation accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by integrating the difference signal over the entire clock period before making the bit level decision. This means the evaluation process accumulates information about the signal level throughout the clock period rather than relying on a single instantaneous measurement, thereby preparing a more robust basis for accurate bit level determination despite transient distortions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by continuously integrating the difference signal throughout the entire clock period. This continuous accumulation of signal information ensures that transient distortions like glitches and crosstalk do not disproportionately affect the final evaluation, as the integration process averages out these temporary anomalies over the complete measurement interval

Inventive Principle:
Principle #20Continuity of useful action

2Adaptability or versatility

If the DUT driver is designed for long cable connections, then the adaptability is improved, but the manufacturing precision deteriorates due to signal distortions like ringing, overshoot, and reflections

Engineering Contradiction:
Improvecable length adaptabilityVSAvoidsignal quality
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent converts the harmful effect of signal distortions into a beneficial evaluation process by integrating the difference signal over the entire clock period. The integration process transforms transient distortions like ringing, overshoot, and reflections into averaged values that do not disproportionately affect the final bit level decision, thereby maintaining manufacturing precision despite long cable connections

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the evaluation parameter from instantaneous voltage level comparison to time-integrated difference signal evaluation. This parameter transformation allows the system to tolerate signal quality degradation from long cable connections while maintaining accurate bit level evaluation through the accumulated information over the complete clock period

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8378707B2Evaluation of an output signal of a device under test
Publication Date: 2013.02.19 ADVANTEST CORP
  • US8378707B2 patent drawing
  • US8378707B2 patent drawing
  • US8378707B2 patent drawing

AI summary

The present invention relates to a method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, said method including the steps of: generating a difference signal representing the difference between said output signal of said Device Under Test and a reference signal, integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.