Parallel DUT Testing via Capacitance-Based Load Balancing
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Solution Overview
Problem
Current testing methods for devices under test (DUT) are inefficient, resulting in prolonged testing periods that hinder production efficiency in the electronics industry.
Innovation Solution
A system and method that utilize multiple test cores in parallel, with a computer device allocating test quantities and capacitance values to evenly distribute the testing load, employing allocation strategies such as to-and-fro, odd-even, and random average methods to optimize testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-core testing method is used, then testing can be completed with simple equipment, but testing period is prolonged and production efficiency is reduced
Solution Approach 1:
The patent divides the testing function into multiple independent test cores (first test core, second test core, third test core, etc.), each capable of independently testing different test parameters. This segmentation allows parallel testing to occur, significantly reducing the overall testing period while maintaining comprehensive test coverage.
Solution Approach 2:
The patent transitions from sequential single-core testing to parallel multi-core testing by adding the dimension of concurrency. Multiple test cores operate simultaneously on different test parameters, transforming the testing process from a one-dimensional sequential operation to a multi-dimensional parallel operation, thereby dramatically improving productivity.
2Loss of time
If multiple test cores are used in parallel, then testing time is reduced, but workload distribution imbalance may occur
Solution Approach 1:
The patent performs preliminary classification and ranking of test parameters based on their capacitance values before distributing them to test cores. By pre-sorting test parameters and allocating them in advance, the system ensures balanced workload distribution across all test cores, preventing any single core from being overloaded or underutilized during parallel testing.
Solution Approach 2:
The patent implements a feedback mechanism where the computer device calculates total capacitance values for different test parameters, classifies and ranks them, and then distributes them to achieve equalization of workload across test cores. This feedback-based allocation ensures that each test core receives a balanced amount of work, optimizing parallel testing efficiency.
3Device complexity
If test parameters are not classified by capacitance value, then allocation is simpler, but workload imbalance occurs across test cores
Solution Approach 1:
The patent performs preliminary classification and ranking of test parameters based on their capacitance values before distributing them to test cores. By pre-sorting test parameters and allocating them in advance, the system ensures balanced workload distribution across all test cores, preventing any single core from being overloaded or underutilized during parallel testing.
Solution Approach 2:
The patent changes the allocation strategy from random or simple sequential distribution to capacitance-based classified allocation. By using capacitance values as the basis for classification and ranking, the system transforms the allocation process into a parameter-driven approach that automatically balances workload, improving testing efficiency without significantly increasing system complexity.
Data Source
AI summary
The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.