DUT Structures for Voltage Contrast Contact Open Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods fail to reliably detect contact opens between epitaxial silicon and contact metal in integrated circuits, particularly due to the buried nature of these defects, which are difficult to detect inline and often lead to yield losses and increased costs.
Innovation Solution
The use of dummy device under test (DUT) structures that employ voltage contrast (VC) mode to detect electrical opens/shorts between contacts and epitaxial silicon, allowing for inline, non-destructive detection of defects using specialized DUT structures fabricated alongside active structures on a test wafer, where grounded features appear bright and floated ones appear darker in VC images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional detection methods are used, then manufacturing process is simple, but contact opens cannot be reliably detected leading to yield losses
Solution Approach 1:
The patent introduces an intermediary DUT structure that includes a dummy gate and dummy contact, which acts as a mediator to enable VC detection of contact opens. The dummy gate is positioned adjacent to the dummy contact, creating a test structure that allows voltage contrast imaging to detect contact opens between the dummy contact and the epi layer, thereby improving detection reliability without complicating the actual device fabrication
Solution Approach 2:
The patent creates a copy of the actual device structure in the form of a DUT (Device Under Test) structure. The DUT includes a dummy gate and dummy contact that replicate the essential features of the actual device, allowing VC detection to be performed on the copy rather than the production device. This copying approach enables reliable defect detection while keeping the production process unchanged
2Loss of time
If inline detection is implemented, then yield learning time is reduced, but detection method complexity increases
Solution Approach 1:
The patent implements preliminary action by incorporating DUT structures with dummy gates and dummy contacts into the fabrication process before production devices are completed. The VC detection is performed inline during the manufacturing process, allowing contact opens to be detected early rather than requiring end-of-line testing. This preliminary detection approach reduces yield learning time by 5-6 weeks as stated in the patent
Solution Approach 2:
The patent replaces conventional mechanical or electrical detection methods with voltage contrast (VC) imaging technology. VC mode uses electron beam imaging to detect voltage differences, substituting traditional contact-based measurement methods. This substitution enables non-destructive, inline detection of contact opens that were previously difficult or impossible to detect without destroying the device
3Ease of operation
If VC mode is used for detection, then contact opens can be detected non-destructively, but specialized DUT structures are required
Solution Approach 1:
The patent applies local quality by creating specialized DUT structures with specific local features (dummy gate adjacent to dummy contact) that are different from the main production devices. The dummy gate is positioned in close proximity to the dummy contact, creating a localized test structure that is optimized for VC detection. This local modification approach allows VC detection to work effectively without requiring complete redesign of the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables early detection of contact opens, reducing yield learning time by 5-6 weeks, minimizing end-of-line testing, and establishing correlations with known yield signals, thereby enhancing manufacturing yield and reducing costs.
Implementation Method 1
dummy device under test (DUT) structures that employ voltage contrast (VC) mode to detect electrical opens/shorts between contacts and epitaxial silicon
Data Source
AI summary
A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.