Duty Adjustment Circuit With Feedback Delay Compensation
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Solution Overview
Problem
Existing duty adjustment circuits in semiconductor storage devices face challenges in maintaining accurate duty cycle adjustments, leading to reliability issues due to variations in delay element performance and environmental fluctuations.
Innovation Solution
A duty adjustment circuit comprising multiple delay circuits with variable delay units, where the output of the second delay circuit is connected to even-numbered delay elements and the output of the third delay circuit is connected to odd-numbered delay elements, allowing for precise adjustment of clock signals by generating and correcting duty cycles through a DCD circuit, arithmetic circuit, and waveform generation circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a duty adjustment circuit uses delay elements to adjust clock duty cycles, then the duty cycle can be modified, but variations in delay element performance and environmental fluctuations cause inaccuracies in the adjustment
Solution Approach 1:
The patent implements a feedback mechanism where the output clock signal is fed back to the delay adjustment circuit, which continuously monitors and adjusts the delay amounts based on the actual output duty cycle. This closed-loop control compensates for variations in delay element performance and environmental fluctuations, maintaining accurate duty cycle adjustment despite component tolerances and temperature/voltage changes.
Solution Approach 2:
The patent dynamically changes the delay parameter by adjusting the delay amount in response to detected duty cycle deviations. The circuit modifies the delay characteristic of the delay elements based on feedback signals, enabling adaptive compensation for environmental variations and maintaining precise duty cycle control under changing operating conditions.
2Measurement precision
If multiple delay circuits are used to adjust duty cycles, then adjustment precision can be improved, but the circuit complexity increases
Solution Approach 1:
The patent divides the duty cycle adjustment function into multiple independent delay circuits, each responsible for adjusting specific portions of the clock signal cycle. This segmentation allows precise control of different time intervals within the clock period while maintaining modular circuit architecture that simplifies design and analysis compared to a single complex delay circuit.
Solution Approach 2:
The patent designs the delay circuits to perform multiple functions: they provide both the primary duty cycle adjustment and serve as the basis for feedback control. The same delay elements used for adjustment are also monitored to detect actual output characteristics, eliminating the need for separate measurement circuits and reducing overall system complexity.
Data Source
AI summary
According to one embodiment, a duty adjustment circuit includes: a first delay circuit including a plurality of first delay elements connected in series, each of the first delay elements has a first delay amount; a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount; and a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount. An output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.