Duty Adjustment Circuit for Stable DLL Clock Duty Correction
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Solution Overview
Problem
Existing duty adjustment circuits in delay locked loop circuits face challenges in accurately correcting the duty cycle of output clock signals across varying frequencies, voltages, and temperatures, leading to instability and inefficiency in semiconductor memory devices.
Innovation Solution
A duty adjustment circuit comprising a pulse generator, code generator, and duty adjuster that generates a pulse signal with constant width regardless of reference clock frequency, and adjusts the slope of rising and falling transitions of the delay clock signal based on generated codes to correct the duty cycle, ensuring accurate duty cycle correction across frequency, voltage, and temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional duty adjustment circuit is used to correct the duty cycle of output clock signals, then the duty cycle can be adjusted, but the correction accuracy deteriorates when frequency, voltage, or temperature changes occur
Solution Approach 1:
The duty adjustment circuit dynamically adapts its correction amount based on detected operating conditions (frequency, voltage, temperature). The circuit modifies its correction behavior in real-time according to the detected environment, rather than using a fixed correction mechanism, thereby maintaining accuracy across varying conditions.
Solution Approach 2:
The circuit changes its correction parameters based on detected operating conditions. When frequency, voltage, or temperature is detected to be outside a reference range, the circuit adjusts the correction amount accordingly, using different correction values for different operating conditions to maintain optimal duty cycle accuracy.
2Reliability
If the duty adjustment circuit uses a fixed correction mechanism, then the circuit structure remains simple, but the correction accuracy deteriorates under varying environmental conditions
Solution Approach 1:
The duty adjustment circuit incorporates a detection mechanism that monitors operating conditions (frequency, voltage, temperature) and provides feedback to the correction mechanism. This feedback loop enables the circuit to automatically adjust its correction behavior based on actual operating conditions, improving reliability without requiring complex external control systems.
Solution Approach 2:
The duty adjustment circuit performs self-adjustment based on its own detection of operating conditions. The circuit independently detects frequency, voltage, and temperature variations and automatically modifies its correction amount accordingly, without requiring external intervention or complex control infrastructure.
Data Source
AI summary
A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.